CMOS imager with selectively silicided gates
View Patent ↗The invention also relates to an apparatus and method for selectively providing a silicide coating over the transistor gates of a CMOS imager to improve the speed of the transistor gates. The method further includes an apparatus and method for forming a self aligned photo shield over the CMOS imager.
1. An imager comprising:
a substrate doped to a first conductivity type;
at least one pixel cell comprising:
a photocollection region within said substrate, wherein said photocollection region is doped to a second conductivity type and comprises a photogate;
at least one transistor gate over said substrate; and
an opaque conductive material over said substrate, said opaque conductive material only partially covering said transistor gate and said photogate; and
a signal processing circuit on said substrate, wherein said circuit is connectable to said at least one pixel cell.
2. The imager according to claim 1 , wherein said opaque conductive material is an opaque conductive silicide.
3. The imager according to claim 2 , wherein said opaque conductive silicide is one of a tungsten silicide, a titanium silicide, a cobalt silicide, and a molybdenum silicide.
4. The imager according to claim 1 , wherein said opaque conductive material is an opaque conductive barrier metal.
5. The imager according to claim 4 , wherein said opaque conductive barrier metal is one of TiN/W layer, WNx/W layer, and WNx.
6. The imager according to claim 1 , wherein said transistor gate is part of a transistor which is one or more of a reset transistor, a row select transistor, source follower transistor or a transfer transistor.
7. The imager according to claim 6 , wherein said transistor gate is part of a transistor which is a reset transistor, said imager further comprising a transfer transistor which includes an opaque conductive material deposited over the gate region of said transfer transistor.
8. The imager according to claim 1 , wherein said imager further includes a thin ring of opaque conductive material formed over the outer periphery of said photogate.
9. A processing system comprising:
a processor; and
an imaging device coupled to said processor and including:
a substrate doped to a first conductivity type;
at least one pixel cell comprising:
a photocollection region within said substrate, wherein said photocollection region is doped to a second conductivity type and comprises a photogate;
at least one transistor gate over said substrate; and
an opaque conductive material over said substrate, said opaque conductive material only partially covering said transistor gate and said photogate; and
a signal processing circuit on said substrate, wherein said circuit is connectable to said at least one pixel cell.
10. The system according to claim 9 , wherein said opaque conductive material is an opaque conductive silicide.
11. The system according to claim 9 , wherein said opaque conductive material is an opaque conductive barrier metal.
12. The system according to claim 9 , wherein said transistor gate is part of a transistor which is one or more of a reset transistor, a row select transistor, source follower transistor, amplifier transistor or a transfer transistor.
13. The system according to claim 9 , wherein said imager further includes a thin ring of opaque conductive material formed over the outer periphery of said photogate.