Zero power chip standby mode
View Patent ↗A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.
1. A system comprising:
a processor;
a power supply coupled to the processor; and
a memory device coupled to the processor and the power supply and comprising:
a pad configured to receive a power signal;
an internal power supply bus configured to receive the power signal from the power supply;
an isolation circuit configured to disconnect the internal power supply bus from the power supply by interrupting the flow of the power signal when a standby mode is indicated by a control signal received at the isolation circuit, wherein the isolation circuit is coupled between the pad on the device and the internal power supply bus;
an input buffer coupled to the isolation circuit via a control line, the control line configured to provide the control signal to the isolation circuit; and
circuitry coupled to the pad and isolation circuit and configured to receive the power signal regardless of whether the standby mode is indicated by the control signal.
2. The system, as set forth in claim 1 , wherein the system is a cellular phone.
3. The system, as set forth in claim 1 , wherein the system is a personalized digital assistant (PDA).
4. The system, as set forth in claim 1 , wherein the system is a handheld computer.
5. The system, as set forth in claim 1 , wherein the isolation circuit comprises a p-channel field effect transistor (FET).
6. The system, as set forth in claim 5 , wherein the gate of the p-channel FET is coupled to the control line of the input buffer.
7. The system, as set forth in claim 1 , comprising an output buffer configured to buffer the device from the remainder of the system.
8. The system, as set forth in claim 7 , comprising:
an input/output pad; and
wherein the circuitry is coupled between the output buffer and the input/output pad and configured to tri-state the input/output pad.