High density dynamic ternary-CAM memory architecture
View Patent ↗A ternary CAM memory device is disclosed which comprises a pair of complementary compare lines, a pair of complementary bit lines, and a unique four transistor two capacitor circuit.
1. A method of producing a CAM cell, comprising:
forming a bit line, compare line, and match line over a substrate;
forming a first and second switch;
forming a storage area; and
electrically coupling said bit line to one of a source/drain area of said first switch, the other source/drain area of said first switch to said storage area, said compare line to one of a source/drain area of said second switch, the other source/drain area of said second switch to said match line, and the gate of said second switch to said storage area.
2. The method of claim 1 further comprising forming a word line, and electrically coupling a gate of said first switch to said word line.
3. The method of claim 1 , wherein said forming a storage area comprises forming a capacitor.
4. The method of claim 1 , wherein said forming a storage area comprises forming a transistor.
5. The method of claim 1 , further comprising:
forming over said substrate a second bit line which is complementary to said bit line, and a second compare line which is complementary to said compare line;
forming a third and fourth switch;
forming a second storage area; and
electrically coupling said second bit line to one of a source/drain area of said third switch, the other source/drain area of said third switch to said second storage area, said second compare line to one of a source/drain area of said fourth switch, the other source/drain area of said fourth switch to said match line, and the gate of said fourth switch to said second storage area.
6. A method of producing a CAM device, comprising:
forming a plurality of CAM cells, where forming one of said plurality of CAM cells comprises:
forming a first bit line, first compare line, and match line over a substrate;
forming a first storage area;
forming a first and second switch; and
electrically coupling said first bit line to one of a source/drain area of said first switch, the other source/drain area of said first switch to said first storage area, said first compare line to one of a source/drain area of said second switch, the other source/drain area of said second switch to said match line, and the gate of said second switch to said first storage area.
7. The method of claim 6 further comprising forming a word line, where a gate of said first switch is electrically coupled to said word line.
8. The method of claim 6 , wherein said forming a storage area comprises forming a capacitor.
9. The method of claim 6 , wherein said forming a storage area comprises forming a transistor.
10. The method of claim 6 , wherein said method of forming a CAM cell further comprises:
forming over said substrate a second bit line which is a complement to said first bit line and a second compare line which is a complement to said first compare line;
forming a third and fourth switch;
forming a second storage area; and
electrically coupling said second bit line to one of a source/drain area of said third switch, the other source/drain area of said third switch to said second storage area, said second compare line to one of a source/drain area of said fourth switch, the other source/drain area of said fourth switch to said match line, the gate of said fourth sixth to said second storage area.