High speed data bus
View Patent ↗The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.
1. A state decoder circuit comprising:
a state decoder configured to receive an address signal targeted for a memory circuit and having an input coupled to memory control signals and an output;
wherein the state decoder is configured to have an output signal having a first state during a memory access and a second state in the absence of a memory access;
wherein the state decoder is configured to activate a switch to decouple a memory circuit from a data bus when no memory access cycle is being performed; and
wherein a memory controller receives the memory control signals and controls the memory access.
2. The state decoder circuit of claim 1 wherein the address signal comprises a row address strobe signal.
3. The state decoder circuit of claim 1 wherein the address signal comprises a column address strobe signal.
4. The state decoder circuit of claim 1 wherein the state decoder is integrated with a printed circuit board.
5. The state decoder circuit of claim 4 , wherein the printed circuit board is integrated with the memory circuit.
6. The state decoder circuit of claim 5 wherein the memory circuit comprises synchronous-DRAM memory.
7. A switch comprising:
a plurality of inputs connected to corresponding ones of a plurality of electrical contacts, and a plurality of outputs connected to at least one memory integrated circuit so as to couple a data bus from the plurality of electrical contacts to the memory integrated circuit, the at least one switch having an additional input coupled to a state decoder circuit output that is responsive to an address signal, and responsive to the state decoder circuit output to decouple the memory circuit from the data bus when no memory access cycle is being performed, wherein a memory controller controls the memory access cycle.
8. The switch of claim 7 wherein the switch is integrated with a printed circuit board.
9. The switch of claim 7 wherein the switch is integrated with the memory integrated circuit.
10. The switch of claim 7 wherein memory integrated circuits comprise a state decoder circuit.
11. The switch of claim 7 wherein the memory integrated circuits comprise synchronous-DRAM memory.
12. The switch of claim 7 wherein the address signal comprises a row address strobe signal.
13. The switch of claim 7 wherein the address signal comprises a column address strobe signal.