Semiconductor memory circuitry
View Patent ↗Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. Considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M, and 256M integration levels. Further, an integrated circuit includes a semiconductor die, a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die, and circuitry formed on the semiconductor die and coupled to the memory cells for permitting data to be written to and read from the memory cells, wherein at least one area of 100 square microns of continuous surface area of the die has at least 170 of the memory cells.
1. An integrated circuit comprising:
a semiconductor die;
a plurality of functional and operably addressable memory cells arranged in at least one array formed on the semiconductor die; and
circuitry formed on the semiconductor die and coupled to the plurality of functional and operably adressable memory cells for permitting data to be written to and read from the plurality of functional and operably addressable memory cells;
wherein at least one area of 100-square microns of continuous surface area of the semiconductor die has at least 170 of the memory cells.
2. The integrated circuit as claimed in claim 1 , wherein the circuitry formed on the semiconductor die and coupled to the plurality of functional and operably adressable memory cells for permitting data to be written to and read from the plurality of functional and operably addressable memory cells includes column addressing circuitry for addressing columns of the plurality of functional and operably addressable memory cells, and sense amplifier circuitry for sensing signals from rows of the plurality of functional and operably addressable memory cells.
3. The integrated circuit as claimed in claim 1 , wherein the plurality of functional and operably addressable memory cells are dynamic random access memory cells.
4. The integrated circuit as claimed in claim 1 , wherein at least 67,108,864 functional and operably addressable memory cells are formed on the semiconductor die.
5. The integrated circuit as claimed in claim 1 , wherein at least 67,108,864 and no more than 68,000,000 functional and operably addressable memory cells are formed on the semiconductor die.
6. The integrated circuit as claimed in claim 5 , wherein all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 40 mm 2 .
7. The integrated circuit as claimed in claim 1 , wherein at least 16,777,216 functional and operably addressable memory cells are formed on the semiconductor die.
8. The integrated circuit as claimed in claim 1 , wherein at least 4,194,394 functional and operably addressable memory cells are formed on the semiconductor die.
9. The integrated circuit as claimed in claim 8 , wherein all of the functional and operably addressable memory cells formed on the semiconductor die have a combined area on the semiconductor die that is no greater than 2.5 mm 2 .
10. An integrated circuit comprising:
a semiconductor die;
a plurality of functional and operably addressable dynamic random access memory cells arranged in at least one array formed on the semiconductor die;
column addressing circuitry formed on the semiconductor die and coupled to the plurality of functional and operably addressable dynamic random access memory cells for addressing columns of the plurality of functional and operably addressable dynamic random access memory cells, and
sense amplifier circuitry formed on the semiconductor die and coupled to the plurality of functional and operably addressable dynamic random access memory cells for sensing signals from rows of the plurality of functional and operably addressable dynamic random access memory cells;
wherein at least one area of 100-square microns of continuous surface area of the semiconductor die has at least 170 of the plurality of functional and operably addressable dynamic random access memory cells.
11. The integrated circuit as claimed in claim 10 , wherein at least 67,108,864 functional and operably addressable memory cells are formed on the semiconductor die.
12. A plurality of integrated circuits comprising:
a processed semiconductor wafer ready for dicing; and
a plurality of die sites on the processed semiconductor wafer;
wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include a plurality of functional and operably addressable memory cells arranged in at least one array, circuitry coupled to the plurality of functional and operably addressable memory cells for permitting data to be written to and read from the plurality of functional and operably addressable memory cells, and at least one area of 100-square microns of continuous surface area of the processed semiconductor wafer having at least 170 of the plurality of functional and operably addressable memory cells.
13. The plurality of integrated circuits as claimed in claim 12 , wherein the circuitry coupled to the plurality of functional and operably addressable memory cells for permitting data to be written to and read from the memory cells includes column addressing circuitry for addressing columns of the plurality of functional and operably addressable memory cells, and sense amplifier circuitry for sensing signals from rows of the plurality of functional and operably addressable memory cells.
14. The plurality of integrated circuits as claimed in claim 12 , wherein the plurality of functional and operably addressable memory cells are dynamic random access memory cells.
15. The plurality of integrated circuits as claimed in claim 12 , wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include at least 256,000,000 functional and operably addressable memory cells.
16. The plurality of integrated circuits as claimed in claim 12 , wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include at least 256,000,000 and no more than 275,000,000 functional and operably addressable memory cells.
17. The plurality of integrated circuits as claimed in claim 16 , wherein the processed semiconductor wafer has a major diameter of about 12 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 210.
18. The plurality of integrated circuits as claimed in claim 16 , wherein the processed semiconductor wafer has a major diameter of about 8 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 86.
19. The plurality of integrated circuits as claimed in claim 16 , wherein the processed semiconductor wafer has a major diameter of about 6 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 45.
20. The plurality of integrated circuits as claimed in claim 12 , wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include at least 64,000,000 functional and operably addressable memory cells.
21. The plurality of integrated circuits as claimed in claim 20 , wherein the processed semiconductor wafer has a major diameter of about 12 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 525.
22. The plurality of integrated circuits as claimed in claim 20 , wherein the processed semiconductor wafer has a major diameter of about 8 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 200.
23. The plurality of integrated circuits as claimed in claim 20 , wherein the processed semiconductor wafer has a major diameter of about 6 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 100.
24. The plurality of integrated circuits as claimed in claim 12 , wherein a predominant number of the total number of plurality of die sites on the processed semiconductor wafer include at least 16,000,000 functional and operably addressable memory cells.
25. The plurality of integrated circuits as claimed in claim 24 , wherein the processed semiconductor wafer has a major diameter of about 12 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 1780.
26. The plurality of integrated circuits as claimed in claim 24 , wherein the processed semiconductor wafer has a major diameter of about 8 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 700.
27. The plurality of integrated circuits as claimed in claim 24 , wherein the processed semiconductor wafer has a major diameter of about 6 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 375.
28. The plurality of integrated circuits as claimed in claim 12 , wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include at least 4,000,000 functional and operably addressable memory cells.
29. The plurality of integrated circuits as claimed in claim 28 , wherein the processed semiconductor wafer has a major diameter of about 12 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 5,975.
30. The plurality of integrated circuits as claimed in claim 28 , wherein the processed semiconductor wafer has a major diameter of about 8 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 2,500.
31. The plurality of integrated circuits as claimed in claim 28 , wherein the processed semiconductor wafer has a major diameter of about 6 inches, and the total number of the plurality of die sites on the processed semiconductor wafer is at least 1,300.
32. A plurality of integrated circuits comprising:
a processed semiconductor wafer ready for dicing; and
a plurality of die sites on the processed semiconductor wafer;
wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include a plurality of functional and operably addressable dynamic random access memory cells arranged in at least one array, column addressing circuitry coupled to the plurality of functional and operably addressable dynamic random access memory cells for addressing columns of the plurality of functional and operably addressable dynamic random access memory cells, sense amplifier circuitry coupled to the plurality of functional and operably addressable dynamic random access memory cells for sensing signals from rows of the plurality of functional and addressable dynamic random access memory cells, and at least one area of 100-square microns of continuous surface area of the processed semiconductor wafer having at least 170 of the plurality of functional and operably addressable dynamic random access memory cells.
33. The plurality of integrated circuits as claimed in claim 32 , wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include at least 256,000,000 functional and operably addressable memory cells.
34. The plurality of integrated circuits as claimed in claim 32 , wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include at least 256,000,000 and no more than 275,000,000 functional and operably addressable memory cells.
35. The plurality of integrated circuits as claimed in claim 32 , wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include at least 64,000,000 functional and operably addressable memory cells.
36. The plurality of integrated circuits as claimed in claim 32 , wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include at least 16,000,000 functional and operably addressable memory cells.
37. The plurality of integrated circuits as claimed in claim 32 , wherein a predominant number of the total number of the plurality of die sites on the processed semiconductor wafer include at least 4,000,000 functional and operably addressable memory cells.