Low current wide VREF range input buffer
View Patent ↗A low-current input buffer is disclosed. The buffer uses self-biased N and P channel differential pairs with their outputs tied together. The self-biasing assists in reducing current consumption. The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages.
1. A differential input buffer, comprising:
a buffer circuit having separate p- and n-channel differential amplifiers arranged to each receive a pair of input signals, said p- and n-channel differential amplifiers each being self-biased;
a shared enable transistor, wherein said p- and n-channel differential amplifiers are each coupled to said shared enable transistor; and
an output terminal for combining the outputs of said p- and n-channel differential amplifiers to form an output of said differential input buffer.
2. The input buffer of claim 1 , wherein said shared enable transistor is coupled to ground.
3. The input buffer of claim 1 , wherein said shared enable transistor is coupled to a supply voltage.
4. The input buffer of claim 1 , wherein said shared said enable transistor is coupled to ground, and wherein said p- and n-channel differential amplifiers each have a separate enable transistor coupled to a supply voltage terminal.
5. The input buffer of claim 1 , wherein said shared enable transistor is coupled to a supply voltage, and wherein said p- and n-channel differential amplifiers each have a respective enable transistor coupled to a ground terminal.
6. The input buffer of claim 1 , wherein said shared enable transistor is coupled to a ground terminal and wherein said p- and n-channel differential amplifiers are each coupled to a second shared enable transistor which is coupled to a supply voltage terminal.
7. The input buffer of claim 1 , wherein said shared enable transistor is coupled to a supply voltage terminal, while one of said differential amplifiers has an enable transistor coupled to ground and the other of said differential amplifiers is directly connected to ground.
8. A processing system circuit, comprising:
a processor; and
a memory circuit for exchanging data with said processor;
at least one of said processor and memory circuit comprising an input buffer circuit, said input buffer circuit further comprising:
a buffer circuit having separate p- and n-channel differential amplifiers; wherein said separate p- and n-channel differential amplifiers are each self-biased;
a shared enable transistor, wherein said p- and n-channel differential amplifiers are each coupled to said shared enable transistor, and
wherein the outputs of said p- and n-channel differential amplifiers are combined to form an output of said differential input buffer.
9. The processor circuit of claim 8 , wherein said shared enable transistor is an n-channel enable transistor coupled to a ground terminal.
10. The processor circuit of claim 8 , wherein said shared enable transistor is a p-channel enable transistor coupled to a supply voltage terminal.
11. The processor circuit of claim 8 , wherein said shared enable transistor is an n-channel enable transistor coupled to ground, and wherein said p- and n-channel differential amplifiers each have a separate p-channel enable transistor coupled to a supply voltage terminal.
12. The processor circuit of claim 8 , wherein said shared enable transistor is a p-channel enable transistor coupled to a supply voltage terminal, and wherein said p- and n-channel differential amplifiers each have a separate n-channel enable transistor coupled to a ground terminal.
13. The processor circuit of claim 8 , wherein said shared enable transistor is an n-channel enable transistor coupled to a ground terminal and wherein said p- and n-channel differential amplifiers are coupled to a shared p-channel enable transistor which is coupled to a supply voltage terminal.
14. The processor circuit of claim 8 , wherein said shared enable transistor is coupled to a ground terminal and wherein said p- and n-channel differential amplifiers are each directly connected to a supply voltage terminal.
15. The processor circuit of claim 8 , wherein shared enable transistor is coupled to a supply voltage terminal and wherein said p- and n-channel differential amplifiers are each directly connected to a ground terminal.
16. The processor circuit of claim 8 , wherein said shared enable transistor is coupled to a supply voltage terminal, and wherein one of said differential amplifiers has an enable transistor coupled to ground and the other of said differential amplifiers is directly connected to ground.
17. A method of operating a input buffer, comprising:
self-biasing a pair of separate p- and n-channel differential amplifiers;
enabling said pair of p- and n-channel differential amplifiers, wherein said p- and n-channel differential amplifiers are coupled to a shared enable transistor;
detecting an input signal;
comparing said input signal with a reference signal using said p- and n-channel differential amplifiers; and
emitting the results of said comparison as an output signal.
18. The method of claim 17 , wherein said shared enable transistor is an n-channel enable transistor coupled to ground.
19. The method of claim 17 , wherein said shared enable transistor is a p-channel enable transistor coupled to a voltage supply.
20. The method of claim 17 , wherein said shared enable transistor is an n-channel enable transistor coupled to ground, and wherein said p- and n-channel differential amplifiers each have a separate p-channel enable transistor coupled to a supply voltage.
21. The method of claim 17 , wherein said shared enable transistor is a p-channel enable transistor coupled to a supply voltage, and wherein said p- and n-channel differential amplifiers each have a separate n-channel enable transistor coupled to ground.
22. The method of claim 17 , wherein said shared enable transistor is an n-channel enable transistor coupled to ground, and wherein said p- and n-channel differential amplifiers are coupled to a second shared enable transistor, wherein said second shared enable transistor is a p-channel enable transistor coupled to a supply voltage.
23. The method of claim 17 , wherein said shared enable transistor is coupled to ground and wherein said p- and n-channel differential amplifiers are directly connected to a supply voltage.
24. The method of claim 17 , wherein said shared enable transistor is coupled to a supply voltage and wherein said p- and n- channel differential amplifiers are directly connected to ground.
25. The method of claim 17 , wherein said shared enable transistor is coupled to a supply voltage, and wherein one of said differential amplifiers has an enable transistor coupled to ground and the other of said differential amplifiers is directly connected to ground.
26. A differential input buffer, comprising:
a buffer circuit having separate p- and n-channel differential amplifiers arranged to each receive a pair of input signals, said p- and n-channel differential amplifiers each being fully self biased;
an output terminal for combining the outputs of said p- and n-channel differential amplifiers to form an output of said differential input buffer; and
a mirror p-channel differential amplifier coupled to said p-channel differential amplifier and a mirror n-channel differential amplifier coupled to said n-channel differential amplifier, wherein the outputs of said mirror p-channel and n-channel differential amplifiers are coupled to a complementary output terminal to form a complementary output of said differential input buffer.