Sequential nibble burst ordering for data
View Patent ↗Methods of operating a memory device comprised of a plurality of arrays of memory cells and peripheral devices for reading and writing information to the memory cells. One method comprises outputting an n-bit word in two ½n bit prefetch steps from a plurality of memory arrays in response to an address bit. Another method comprises prefetching a first portion of a word from a memory array, and prefetching a second portion of the word from the memory array, the first and second portions being determined by an address bit. Another method comprises reading a word from a memory array in at least two prefetch operations, wherein the order of the prefetch operations is controlled by an address bit.
1. A method, comprising:
outputting in a sequential mode an n-bit word in two ½n bit prefetch steps from a plurality of memory arrays in response to address bits, one of said address bits identifying a starting address and another of said address bits identifying the order of the bits within each of said ½n bit prefetches.
2. The method of claim 1 wherein said one of said address bits and another of said address bits include any of the least significant column address bits.
3. The method of claim 1 additionally comprising writing an n-bit word into one of the plurality of memory arrays in response to said one of said address bits.
4. A method, comprising:
prefetching a first portion of a word from a memory array in a sequential mode of operation;
prefetching a second portion of said word from said memory array in said sequential burst mode of operation, said first and second portions being determined by an address bit; and
reordering the bits of each of said first and second portions in response to other address bits.
5. The method of claim 4 wherein said address bit and said other address bits include any one of the column address bits CA 0 to CA 2 .
6. The method of claim 4 additionally comprising writing an n-bit word into the memory array in response to said address bit.
7. A method, comprising:
reading a word from a memory array in at least two prefetch operations in a sequential mode of operation, wherein the order of said prefetch operations and the order of bits in each prefetch is controlled by address bits.