Balanced data bus inversion
A method and apparatus for balancing an output load using data bus inversion is disclosed. In brief, one such technique comprises measuring the “balance” of data bits across a data bus (e.g., the number of zero values compared to the number of one values in a set of parallel data bits). If the data bits are unbalanced by a specified amount, a portion of the bits on the data bus are inverted, and the data bits, including the inverted portion, are transmitted. Also, a data bus inversion bit is set to a particular value and transmitted with the data bits to indicate that data bus inversion was used. If the data signal is not unbalanced (i.e., the bits on the data bus do not comprise an unbalanced number of logic values), then the bits on the data bus are transmitted as they are detected, and the data bus inversion bit is set to another particular value to indicate that data bus inversion was not used.
1. A data bus inversion algorithm, comprising:
receiving N original data bits, wherein the original data bits comprise one of a logic 0 state and a logic 1 state;
determining whether a number of received logic 0 or logic 1 states of the original data bits is equal to or greater than M; and wherein
if the number of received logic 0 or logic 1 states is equal to or greater than M:
inverting R of the N original data bits to create N encoded data bits, wherein R is less than N;
transmitting the N encoded data bits; and
if the number of received logic 0 or logic 1 states is not equal to or greater than M:
transmitting the N original data bits.
2. The method of claim 1 , wherein if the number of received logic 0 or logic 1 states is equal to or greater than M, transmitting at least one data inversion indicator with the transmitted N encoded data bits.
3. The method of claim 2 , wherein the data inversion indicator comprises a bit.
4. The method of claim 2 , further comprising:
assessing the transmitted at least one data inversion indicator;
if the at least one data inversion indicator is asserted, decoding the N transmitted encoded data bits to recover the N original data bits.
5. The method of claim 4 , wherein decoding the N transmitted encoded data bits comprises uninverting the inverted R original data bits.
6. The method of claim 1 , wherein if the number of received logic 0 or logic 1 states is not equal to or greater than M, failing to transmit a data inversion indicator with the transmitted N original data bits.
7. The method of claim 1 , wherein the inverted R bits comprises half of N.
8. A method for encoding data, comprising:
(a) receiving a plurality of original bits;
(b) determining whether a logic state is predominant in the plurality of original bits; and wherein
(c) if a logic state is predominant in the plurality of original bits:
encoding a portion of the plurality of original bits to form encoded bits, wherein the portion is less than the plurality of original bits;
transmitting the encoded bits along with any non-encoded portion of the original bits; and
(d) if a logic state is not predominant in the plurality of original bits:
transmitting the plurality of original bits without any encoding; and
(e) receiving a next plurality of data bits in at the transmitter to comprise a plurality of original bits, and repeating the above acts (b)-(e).
9. The method of claim 8 , wherein encoding a portion of the plurality of original data bits to form encoded bits comprises inverting the portion of original data bits.
10. The method of claim 8 , wherein the determining is performed by comparing a voltage indicative of the predominance of the logic state to at least one reference voltage.
11. The method of claim 8 , wherein the logic state being predominant comprises at least three-quarters of the plurality of original parallel bits comprising the logic state.
12. The method of claim 8 , wherein the logic state being predominant comprises at more than half of the plurality of original parallel bits comprising the logic state.
13. A method for outputting data, comprising:
(a) receiving a plurality of original bits;
(b) determining a value indicative of the predominance of a logic state in the plurality of original bits; and wherein
(c) comparing the value to a threshold, and depending on this comparison, either
(i) encoding a portion of the plurality of original bits to form encoded bits, wherein the portion is less than the plurality of original bits; and
transmitting the portion of encoded bits, any non-encoded portion of the original bits, and an encoding indicator; or
(ii) transmitting the plurality of original bits without any encoding and without any encoding indicator; and
(d) receiving a next plurality of data bits in at the transmitter to comprise a plurality of original bits, and repeating the above acts (b)-(d).
14. The method of claim 13 , wherein the encoded bits, any non-encoded portion of the original bits, and the encoding indicator, are all transmitted in parallel.
15. The method of claim 13 , wherein encoding comprises performing a data bus inversion algorithm.
16. The method of claim 13 , wherein the encoding indicator comprises a bit that indicates whether a portion of the plurality of original data bits has been encoded.
17. The method of claim 13 , wherein transmitting the plurality of original bits without any encoding indicator comprises transmitting an unasserted encoding indicator.
18. An encoding circuit, comprising:
an input block for receiving original data bits having logic states to be encoded, wherein the input block produces a voltage, wherein the voltage is proportional to the number of asserted original data bit;
an encoding analysis block, wherein the encoding analysis block assesses the voltage to determine whether the logic states in the original data bits are unbalanced; and
encoding circuitry coupled to the encoding analysis block for producing encoded data bits by encoding some, but not all, of the original data bits if the encoding analysis block determines that there is an unbalance in the logic states in the original bits.
19. The encoder of claim 18 , wherein the voltage comprises a fraction of a power supply voltage of the encoder.
20. The encoder of claim 18 , wherein the input block comprises a plurality of switches, each switch for receiving one of the original data bits.
21. The encoder of claim 20 , wherein each switch is coupled to a common load to produce the voltage.
22. The encoder of claim 18 , wherein the encoding analysis block further comprise logic for generating an encoding indicator when there is an unbalance in the logic sates in the original bits.
23. The encoder of claim 22 , further comprising a selector for outputting onto channels onto channels either the original data bits or the encoded data bits depending on the status of the encoding indicator.