IP Library Granted Patent US 6,949,427
Granted Patent B2
US 6,949,427 · App. 10/075,193 · Granted Sep 27, 2005

Methods of forming a capacitor structure

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Quick Facts
Patent No.
US 6,949,427
App. No.
10/075,193
Granted
Sep 27, 2005
Kind
B2
Abstract

The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.

Claims (13)

1. A method of forming a capacitor structure, comprising:

forming a container construction comprising a first silicon-containing layer around a second silicon-containing layer; the first silicon-containing layer being more heavily doped with conductivity-enhancing dopant than the second silicon-containing layer; the second silicon-containing layer defining an exposed inner periphery of the container and the first silicon-containing layer defining an exposed outer periphery of the container;

converting at least some of each of the first and second silicon-containing layers to hemispherical grain silicon; the hemispherical grain silicon from the first silicon-containing layer having a smaller average grain size than the hemispherical grain silicon from the second silicon-containing layer;

forming a dielectric material along the exposed inner and exposed outer peripheries of the container construction, the dielectric material being in direct physical contact with the second silicon-containing layer of the inner periphery and in direct physical contact with the first silicon-containing layer of the outer periphery; and

forming a conductive material over the dielectric material; the container construction, dielectric material and conductive material together defining at least part of the capacitor structure.

2. The method of claim 1 wherein the converting comprises:

(1) exposing the at least some of each of the first and second silicon-containing layers to silane gas and a temperature of at least about 550° C. for a time of less than or equal to about 2 minutes under a vacuum of less than or equal to about 1×10 −4 Torr to seed the at least some of each of the first and second silicon-containing layers; and

(2) annealing the seeded layers at a temperature of at least about 550° C. for a time of less than or equal to about 3 minutes.

3. The method of claim 1 wherein the first silicon-containing layer comprises a dopant concentration of at least 10 20 atoms/cm 3 .

4. The method of claim 1 wherein the first silicon-containing layer comprises a dopant concentration that is at least 10 3 fold higher than any dopant concentration in the second silicon-containing layer.

5. The method of claim 1 wherein the first silicon-containing layer comprises a dopant concentration that is at least 10 5 fold higher than any dopant concentration in the second silicon-containing layer.

6. The method of claim 1 wherein the first silicon-containing layer comprises a dopant concentration that is at least 10 10 fold higher than any dopant concentration in the second silicon-containing layer.

7. The method of claim 1 wherein the second silicon-containing layer is substantially undoped.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2010
From: MICRON TECHNOLOGY, INC.
To: ROUND ROCK RESEARCH, LLC
Reel/Frame 023786/0416 →