Dual mode DDR SDRAM/SGRAM
View Patent ↗A dual-mode dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM). An exemplary DDR SDRAM/SGRAM comprises a single memory device, which itself comprises a memory array including a quad-bank DRAM and a logic circuitry. The logic circuitry is coupled to the memory array and is configurable to operate the single memory device in a first mode and a second mode. The first mode may include a delayed lock loop (DLL) capability while the second mode may include a non-DLL capability.
1. A dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM) comprising a single memory device comprising:
a memory array including a quad-bank DRAM; and
a logic circuitry coupled to the memory array configurable to operate the single memory device in a first mode having delayed lock loop (DLL) capability and in a second mode having non-DLL capability, wherein the logic circuitry comprises an Extended Mode Register adapted to enter the first mode having the DLL capability upon receiving a Load Mode Register command.
2. The DDR SDRAM/SGRAM of claim 1 , wherein the DLL capability provides for alignment of an output data on a read line of the DDR SDRAM/SGRAM with an incoming clock signal.
3. The DDR SDRAM/SGRAM of claim 1 , wherein the single memory device has a plurality of characteristics that vary according to operation in the first mode having the DLL capability compared to operation in the second mode having the non-DLL capability, the plurality of characteristics including at least one characteristic selected from the group essentially consisting of: DLL, CAS latencies, preambles, postambles, set-up timing and hold timing.
4. A dual-data rate (DDR) synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory (SGRAM) comprising a single memory device comprising:
a memory array including a quad-bank DRAM; and
a logic circuitry coupled to the memory array configurable to operate the single memory device in a first mode having delayed lock loop (DLL) capability and in a second mode having non-DLL capability;
wherein the logic circuitry comprises an Extended Mode Register, defaults to the second mode having the non-DLL capability, and enters the first mode having the DLL capability upon receiving a Load Mode Register command on the Extended Mode Register.
5. The DDR SDRAM/SGRAM of claim 4 , wherein the single memory device has a plurality of characteristics that vary according to operation in the first mode having the DLL capability compared to operation in the second mode having the non-DLL capability, the plurality of characteristics including at least one characteristic selected from the group essentially consisting of: DLL, CAS latencies, preambles, postambles, set-up timing and hold timing.
6. The DDR SDRAM/SGRAM of claim 4 , wherein the DLL capability provides for alignment of an output data on a read line of the DDR SDRAM/SGRAM with an incoming clock signal.
7. A memory device for graphics processing comprising:
a memory array including an internal pipelined DRAM;
a logic circuitry coupled to the memory array configurable to operate in a first mode having delayed lock loop (DLL) capability and in a second mode having non-DLL capability;
wherein the DLL capability provides for alignment of an output data on a read line of the memory array with an incoming clock signal; and
wherein the logic circuitry comprises an Extended Mode Register adapted to enter the first mode having the DLL capability upon receiving a Load Mode Register command on the Extended Mode Register.
8. The memory device of claim 7 , wherein the memory device has a plurality of characteristics that vary according to operation in the first mode having the DLL capability compared to operation in the second mode having the non-DLL capability, the plurality of characteristics including at least one characteristic selected from the group essentially consisting of: DLL, CAS latencies, preambles, postambles, set-up timing and hold timing.
9. A memory device for graphics processing comprising:
a memory array including an internal pipelined DRAM;
a logic circuitry coupled to the memory array configurable to operate in a first mode having delayed lock loop (DLL) capability and in a second mode having non-DLL capability,
wherein the DLL capability provides for alignment of an output data on a read line of the memory array with an incoming clock signal; and
wherein the logic circuitry comprises an Extended Mode Register, defaults to the second mode having the non-DLL capability, and enters the first mode having the DLL capability upon receiving a Load Mode Register command on the Extended Mode Register.
10. The memory device of claim 9 , wherein the memory device has a plurality of characteristics that vary according to operation in the first mode having the DLL capability compared to operation in the second mode having the non-DLL capability, the plurality of characteristics including at least one characteristic selected from the group essentially consisting of: DLL, CAS latencies, preambles, postambles, set-up timing and hold timing.
11. A system comprising:
a processor;
a dual-data rate (DDR) memory having a single memory device including a quad-bank DRAM and configurable to operate in a first mode and a second mode, the first mode and the second mode each relating to a different alignment of output data as to a read line of the memory; and
wherein the logic circuitry comprises an Extended Mode Register adapted to enter the first mode having the DLL capability upon receiving a Load Mode Register command.
12. The system of claim 11 wherein the first mode includes a delayed lock loop (DLL) capability and the second mode includes a non-DLL capability.
13. The system of claim 11 , wherein the first mode includes a phase lock loop (PLL) capability and the second mode includes a non-PLL capability.
14. A dual-data rate (DDR) memory comprising a single memory device comprising:
a memory array including a quad-bank DRAM; and
a logic circuitry coupled to the memory array configurable to operate in a first mode and a second mode, the first mode and the second mode each relating to a different alignment of output data as to a read line of the memory, wherein the logic circuitry comprises an Extended Mode Register adapted to enter the first mode having the DLL capability upon receiving a Load Mode Register command.
15. The DDR memory of claim 14 , wherein the first mode relates to one of a delayed lock loop (DLL) capability and a phase lock loop (PLL) capability.
16. A dual-data rate (DDR) memory device comprising:
a memory array including full page burst capability; and
a logic circuit coupled to the memory array configurable to operate in a first mode and a second mode, the first mode and the second mode each relating to a different alignment of output data as to a read line of the memory device, wherein the logic circuitry comprises an Extended Mode Register adapted to enter the first mode having the DLL capability upon receiving a command.
17. The DDR memory device of claim 16 , wherein the memory device comprises a synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory.
18. A memory device comprising:
a memory array including a quad-bank DRAM having full page burst capability; and
a logic circuit coupled to the memory array and having a capability to align output data as to a read line of the memory device in accordance with a plurality of different modes, wherein the logic circuitry comprises an Extended Mode Register adapted to enter the first mode having the DLL capability upon receiving a command.
19. The memory device of claim 18 , wherein the plurality of different modes includes a delayed lock loop (DLL) mode.
20. The memory device of claim 18 , wherein the plurality of different modes includes a phase lock loop (PLL) mode.
21. The memory device of claim 18 , wherein the plurality of different modes includes two modes.
22. The memory device of claim 18 , wherein the memory device comprises a synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory.
23. A system comprising:
a processor; and,
a dual-data rate (DDR) memory having a single memory device having full page burst capability and a capability to align output data as to a read line of the memory device in accordance with a plurality of different modes, wherein the logic circuitry comprises an Extended Mode Register adapted to enter the first mode having the DLL capability upon receiving a command.
24. The system of claim 23 , wherein the plurality of different modes includes a delayed lock loop (DLL) mode.
25. The system of claim 23 , wherein the plurality of different modes includes a phase lock loop (PLL) mode.
26. The system of claim 23 , wherein the plurality of different modes includes two modes.
27. The system of claim 23 , wherein the memory device comprises a synchronous dynamic random access memory (SDRAM)/synchronous graphic random access memory.