Multiple category CAM
View Patent ↗An apparatus and method is disclosed for a CAM match detection circuit with a multiple category CAM circuit. The multiple category CAM circuit provides category association tables to specify which priority encoders are to be used for certain CAM words of an identified category. By using the assigned categories, priority resolvers may efficiently reallocate packet data according to category (e.g., video, voice, graphics, etc.).
1. A circuit for associating searched CAM words to a category of priority encoders, comprising:
a plurality of bit-for-bit detection circuits, each bit-for-bit detection circuit being associated with a corresponding CAM word for comparing said corresponding CAM word to a comparand, each of said detection circuits having an output terminal;
a plurality of logic gates, each of said plurality of logic gates having one terminal coupled to an output terminal from one of said plurality of bit-for-bit detection circuits; and
a plurality of storage devices associated with each CAM word, each of said storage devices connected to a second terminal of a respective logic gate wherein the plurality of logic gates are adapted to output a category association signal.
2. The circuit according to claim 1 , wherein the logic gates are NAND gates.
3. The circuit according to claim 1 , wherein the storage devices are flip-flops.
4. The circuit according to claim 3 , wherein each flip-flop is adapted to store a stored bit of a CAM priority code for a corresponding CAM word.
5. The circuit according to claim 4 , further comprising a plurality of priority encoders coupled to at least one of a plurality of category association tables for priority encoding a CAM word when the CAM word is a predetermined match with the comparand.
6. A method for categorizing CAM word searches, said method comprising:
conducting bit-for-bit match detection on each of a plurality of CAM words to a comparand, and outputting a result from each CAM word;
processing each output with an associated category circuit, said processing including the performance of logical functions with selected bits of each CAM word; and
generating a category code for each CAM word from said logical functions.
7. The method of claim 6 , wherein the logical function is a NAND function.
8. The method of claim 6 , wherein the selected bits are a stored priority code for a respective CAM word.
9. The method of claim 8 , wherein the method further comprises selecting at least one of a plurality of encoders according to the priority code.
10. A processing system, comprising:
a processing unit;
a memory component coupled to said processing unit, said memory component containing a categorization circuit for a plurality of content addressable memories (CAMs), said categorization circuit comprising:
a plurality of bit-for-bit detection circuits, each bit-for-bit detection circuit being associated with a different CAM word for comparing said different CAM word to a comparand, each of said detection circuits having an output terminal;
a plurality of logic gates, each of said plurality of logic gates having one terminal coupled to an output terminal from one of said plurality of bit-for-bit detection circuits; and
a plurality of storage devices associated with each CAM word, each of said storage devices connected to a second terminal of a respective logic gate, wherein the plurality of logic gates are adapted to output a category association signal.
11. The processing system according to claim 10 , wherein the logic gates are NAND gates.
12. The processing system according to claim 10 , wherein the storage devices are flip-flops.
13. The processing system according claim 12 , wherein each flip-flop is adapted to store a stored bit of a CAM priority code for a corresponding CAM word.
14. The processing system according to claim 13 , further comprising a plurality of priority encoders coupled to at least one of a plurality of category association tables for priority encoding a CAM word when the CAM word is a predetermined match with the comparand.
15. A content addressable memory, comprising:
a plurality of bit-for-bit detection circuits, each bit-for-bit detection circuit being associated with a corresponding CAM word for comparing said corresponding CAM word to a comparand, each of said detection circuits having an output terminal; and
a category priority encoder selectively coupled to an output terminal from each of said plurality of bit-for-bit detection circuits for determining the priority of said bit-for-bit detection circuits belonging to a category having a match.
16. A content addressable memory as claim 15 , further comprising a plurality of storage devices associated with each CAM word.
17. A content addressable memory as claim 15 , further comprising a plurality of category association tables coupled between said each bit-for-bit detection circuit and said category priority encoder for selectively coupling a bit-for-bit detection circuit to a category priority encoder.
18. A content addressable memory as claim 16 , wherein said each category association table is adapted to receive a priority code to determine selectively coupling a bit-for-bit detection circuit to said category priority encoder.
19. A content addressable memory as claim 18 , further comprising a second category priority encoder coupled to an output terminal from each one of said plurality of bit-for-bit detection circuits.
20. A content addressable memory as in claim 19 , wherein each category association table is adapted to receive a second priority code to determine selectively coupling a bit-for-bit detection circuit to said second category priority encoder.