Zero power chip standby mode
View Patent ↗A zero power standby mode in a memory device used in a system, such as a battery powered hand held device. By disconnecting the internal power supply bus on the memory device from the external power supply during standby mode, the junction leakage and gate induced drain leakage can be eliminated to achieve a true zero-power standby mode. A p-channel field effect transistor (FET) may be used to gate the external power supply such that the internal power supply bus on the memory device may be disconnected from the external power supply.
1. A memory device comprising:
an internal power supply bus internal to the memory device and configured to receive a power signal;
an isolation transistor internal to the memory device configured to disconnect the internal power supply bus from the power signal in response to a control signal that corresponds to a power down state;
a pad of the memory device coupled to the isolation transistor and configured to receive the power signal;
an input buffer coupled to the isolation transistor and the pad, the input buffer configured to provide the control signal to a gate of the isolation transistor; and
circuitry coupled to the input buffer and the pad, wherein the input buffer and the circuitry receive the power signal while in the power down state.
2. The memory device, as set forth in claim 1 , wherein the memory device comprises a static random access memory device.
3. The memory device, as set forth in claim 1 , wherein the internal power supply bus is configured to provide the power signal to the memory device.
4. The memory device, as set forth in claim 1 , comprising an input buffer comprises a control line configured to control the isolation transistor.
5. Them memory device, as set forth in claim 4 , wherein the isolation transistor comprises a p-channel field effect transistor (FET).
6. The memory device, as set forth in claim 5 , comprising an input/output pad coupled to the input buffer, the output buffer, the circuitry, and the pad.
7. The memory device, as set forth in claim 6 , wherein the circuit is configured to tri-state the input/output pad.