High speed data bus
View Patent ↗The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.
1. A computer system comprising:
a host processor;
a memory controller;
a memory circuit;
a data bus coupling said memory controller and said memory circuit; and
a switch for decoupling said data bus from said memory circuit when no memory access is being requested by said memory controller so as to reduce the parasitic capacitance of said data bus, wherein the switch is an integrated part of the memory circuit.
2. The computer system of claim 1 comprising a plurality of memory circuits and a corresponding plurality of decoupling means.
3. The computer system of claim 1 , wherein the memory circuit comprises a synchronous DRAM memory.
4. A computer system comprising:
a host processor;
a memory controller;
a memory circuit;
a data bus coupling said memory controller and said memory circuit; and
a switch for decoupling said data bus from said memory circuit when no memory access is being requested by said memory controller so as to reduce the parasitic capacitance of said data bus,
wherein the switch, the memory circuit and the memory controller are integrated into a single circuit.
5. The computer system of claim 4 , additionally comprising a plurality of memory circuits and a corresponding plurality of decoupling means.
6. The computer system of claim 4 , wherein the memory circuit comprises a synchronous DRAM memory.
7. A computer system comprising:
a host processor;
a memory controller;
a memory circuit;
a data bus coupling said memory controller and said memory circuit; and
a switch for decoupling said data bus from said memory circuit when no memory access is being requested by said memory controller so as to reduce the parasitic capacitance of said data bus,
wherein the switch, the memory circuit and the memory controller are integrated into a single circuit.
8. The computer system of claim 7 , comprising a plurality of memory circuits and a corresponding plurality of decoupling means.
9. The computer system of claim 7 , wherein the memory circuit comprises a synchronous DRAM memory.