Metal gate engineering for surface p-channel devices
View Patent ↗A semiconductor device, such as a CMOS device, having gates with a high work function in PMOS regions and low work functions in NMOS regions and a method of producing the same. Using nitrogen implantation or plasma annealing, a low work function W (or CoSi x )/TaSi x N y /GOx/Si gate stack is formed in the NMOS regions while a high work function W (or CoSi x )/Ta 5 Si 3 /GOx/Si gate stack is formed in the PMOS regions. The improved process also eliminates the need for a nitrided GOx which is known to degrade g m (transconductance) performance. The materials of the semiconductor devices exhibit improved adhesion characteristics to adjacent materials and low internal stress.
1. Complimentary semiconductor devices comprising:
a semiconductive substrate;
complimentary NMOS and PMOS doped regions formed in the substrate;
a dielectric layer positioned on the semiconductive substrate; and
an interconnecting layer positioned on the dielectric layer wherein the interconnecting layer comprises a metal silicide having a first work function wherein the metal of the metal silicide is matched with the silicide such that the metal is inhibited from reacting with the dielectric layer and wherein the interconnecting layer overlying the NMOS regions comprises the metal silicide being further nitrided so as to have a second lower work function.
2. The semiconductor devices of claim 1 , wherein the metal is further selected such that the metal silicide and the nitrided metal silicide exhibit improved adhesion to the adjacent layers.
3. The semiconductor devices of claim 1 , further comprising a conductive layer positioned on the interconnecting layer such that the dielectric layer, the interconnecting layer, and the conductive layer together define a gate stack.
4. The semiconductor devices of claim 3 , wherein the conductive layer comprises tungsten.
5. The semiconductor devices of claim 3 , wherein the conductive layer comprises cobalt silicide.
6. The semiconductor devices of claim 3 , wherein the conductive layer comprises nickel silicide.
7. The semiconductor devices of claim 1 , wherein the metal comprises tantalum.
8. The semiconductor devices of claim 1 , wherein the semiconductive substrate comprises silicon and the dielectric layer comprises silicon dioxide.