High speed data bus
View Patent ↗The invention comprises data processing systems and components thereof. Such systems may include a memory controller, a plurality of memory devices, a data bus coupling the memory controller with the plurality of memory devices, and at least one bus switch located in the data bus between the memory controller and one of the plurality of memory devices. Memory integrated circuits and memory modules including at least one switch in the data bus are also provided.
1. A electronic device comprising:
a memory controller;
a bus switch;
a first data bus connecting the memory controller and the bus switch;
a plurality of memory devices including at least a first and a second memory device;
a second data bus connecting the bus switch to the first memory device and a third data bus connecting the bus switch to the second memory device, and
a state decoder configured to receive an address signal targeted for either the first or second memory device, and having an output responsive to the address signal coupled to the bus switch;
wherein the bus switch is configured to couple the first data bus to the second data bus and decouple the first data bus from the third data bus during memory accesses directed to the first memory device.
2. The electronic device of claim 1 wherein the bus switch is configured to couple the first data bus to the third data bus and decouple the first data bus from the second data bus during memory accesses directed to the second memory device.
3. The electronic device of claim 1 wherein the address signal comprises a row address strobe signal.
4. The electronic device of claim 1 wherein the address signal comprises a column address strobe signal.
5. The electronic device of claim 1 wherein the memory devices comprise synchronous-DRAM memory.
6. The electronic device of claim 5 further comprising a printed circuit board.
7. The electronic device of claim 6 wherein the memory controller, the bus switch, and the memory devices are mounted on the printed circuit board.
8. The electronic device of claim 1 wherein the bus switch is integrated with the memory device.
9. The electronic circuit of claim 1 wherein the state decoder is integrated with the memory device.
10. The electronic circuit of claim 1 wherein the address signal comprises a write enable signal.
11. A electronic device comprising:
a memory controller;
a means for switching;
a first connecting means for connecting the memory controller and the means for switching;
a plurality of memory devices including at least a first and a second memory device;
a second connecting means for connecting the means for switching to the first memory device and a third connecting means for connecting the means for switching to the second memory device, and
a means for receiving an address signal targeted for either the first or second memory device, and having an output responsive to the address signal coupled to the means for switching;
wherein the means for switching couples the first connecting means to the second connecting means and decouples the first connecting means from the third connecting means during memory accesses directed to the first memory device.
12. The electronic device of claim 11 wherein the means for switching couples the first connecting means to the third connecting means and decouples the first connecting means from the second connecting means during memory accesses directed to the second memory device.
13. The electronic device of claim 11 wherein the address signal comprises a row address strobe signal.
14. The electronic device of claim 11 wherein the address signal comprises a column address strobe signal.
15. The electronic device of claim 11 wherein the memory devices comprise synchronous-DRAM memory.
16. The electronic device of claim 11 further comprising a printed circuit board.
17. The electronic device of claim 16 wherein the memory controller, the means for switching, and the memory devices are mounted on the printed circuit board.
18. The electronic device of claim 11 wherein the means for switching is integrated with the memory device.
19. The electronic circuit of claim 11 wherein the state decoder is integrated with the memory device.
20. The electronic circuit of claim 11 wherein the address signal comprises a write enable signal.