Memory with address management
View Patent ↗The present invention allows for the reduction in power consumption of memory devices. A memory device in one embodiment prohibits address signal propagation on internal address buses based upon a function being performed by the memory. As such, some, all or none of the externally provided address signals are allowed to transition past address buffer circuitry.
1. A method of operating a memory device comprising:
receiving externally provided control signals to instruct the memory to perform a selected function;
receiving externally provided address signals; and
prohibiting selected ones of the address signals from propagating past one or more external connections and buffer circuits through to internal memory device circuitry based upon the selected function.
2. A method of operating a memory device comprising:
receiving externally provided control signals to instruct the memory to perform a selected function;
receiving externally provided address signals; and
prohibiting selected ones of the address signals from propagating through internal memory device circuitry based upon the selected function;
wherein prohibiting selected ones of the address signals comprises electrically isolating internal bus lines to prohibit signal transitions of the internal bus lines.
3. A method of operating a memory device comprising:
receiving externally provided control signals to instruct the memory to perform a selected function;
receiving externally provided address signals; and
prohibiting selected ones of the address signals from propagating through internal memory device circuitry based upon the selected function;
wherein the function is selected from one of a Read, a Write, an Active, a NOP (no operation), a Load Mode Register, a Burst Terminate, a Precharge, a Deselect, and a Refresh function.
4. The method of claim 3 , wherein at least some of a plurality of column address signals are prohibited from propagating through the internal memory device circuitry while performing the Active function.
5. The method of claim 3 , wherein at least some of a plurality of row address signals are prohibited from propagating through the internal memory device circuitry while performing either the Read or Write functions.
6. The method of claim 3 , wherein row, column and bank address signals are prohibited from propagating through the internal memory device circuitry while performing the NOP function.
7. A method of operating a DRAM comprising:
receiving externally provided control signals to instruct the memory to perform a Read, Write, Active, or NOP (no operation) function;
receiving externally provided row, column and bank address signals; and
prohibiting selected ones of the row, column and bank address signals from propagating through internal DRAM address buses based upon a selected function.
8. The method of claim 7 , wherein at least some of the column address signals are prohibited from propagating through the internal DRAM address buses while performing the Active function.
9. The method of claim 7 , wherein at least some of the row address signals are prohibited from propagating through the internal DRAM address buses while performing either the Read or Write functions.
10. The method of claim 7 , wherein the row, column and bank address signals are prohibited from propagating through the internal DRAM address buses while performing the NOP function.
11. A method of operating a DRAM comprising:
receiving externally provided control signals to instruct the memory to perform a burst terminate function;
receiving externally provided row, column and bank address signals; and
prohibiting selected ones of the row, column and bank address signals from propagating through internal DRAM address buses when performing the Burst Terminate function.
12. The method of claim 11 , wherein the row, column and bank address signals are received with distributed driver circuits and a pass transistor that is turned off to prohibit the selected ones of the row, column and bank address signals from propagating through the internal DRAM address buses.
13. A method of operating a DRAM comprising:
receiving externally provided control signals to instruct the memory to perform a precharge function;
receiving externally provided row, column and bank address signals; and
prohibiting selected ones of the row, column and bank address signals from propagating through internal DRAM address buses when performing the Precharge function.
14. The method of claim 13 , wherein the row, column and bank address signals are received with distributed driver circuits and a pass transistor that is turned off to prohibit the selected ones of the row, column and bank address signals from propagating through the internal DRAM address buses.
15. A method of operating a DRAM comprising:
receiving externally provided control signals to instruct the memory to perform a refresh function;
receiving externally provided row, column and bank address signals; and
prohibiting selected ones of the row, column and bank address signals from propagating from one or more buffer circuits through to internal DRAM address buses when performing the Refresh function.
16. A method of operating a DRAM comprising:
receiving externally provided control signals to instruct the memory to perform a refresh function;
receiving externally provided row, column and bank address signals; and
prohibiting selected ones of the row, column and bank address signals from propagating through internal DRAM address buses when performing the Refresh function;
wherein the row, column and bank address signals are received with distributed driver circuits and a pass transistor that is turned off to prohibit the selected ones of the row, column and bank address signals from propagating through the internal DRAM address buses.