Programming methods for multi-level flash EEPROMs

1. A method for programming a memory cell of an electrically erasable programmable read only memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the memory cell having a threshold voltage selectively configurable into one of at least three programming states, the method comprising:

generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region; and

generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, the gate voltage being ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the gate voltage ramped with a ramping rate, whereby the selected threshold voltage for each programming state is generated by applying a gate voltage with a different final magnitude, wherein the ramping rate is between approximately 5.5 V/ms and approximately 10.5 V/ms.

2. The method of claim 1 , wherein the final magnitude is between approximately 5.5 V and approximately 10.5 V.

3. The method of claim 1 , wherein the drain-to-source bias voltage is substantially constant.

4. The method of claim 1 , wherein the drain-to-source bias voltage comprises at least one voltage pulse having a period.

5. The method of claim 4 , wherein the period is between approximately 1 nanosecond and approximately 10 microseconds.

6. The method of claim 1 , wherein the drain-to-source bias voltage is approximately 5 volts.

7. The method of claim 1 , wherein a transistor comprising a control gate is connected in series between the drain region of the memory cell and a drain voltage generator, whereby a control voltage applied to the control gate of the transistor adjusts a voltage applied to the drain region of the memory cell.

8. A method for programming a memory cell of an electrically erasable programmable read only memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the memory cell having a threshold voltage selectively configurable into one of at least three programming states, the method comprising:

generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region; and

generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, the gate voltage being ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the gate voltage ramped with a ramping rate, whereby the selected threshold voltage for each programming state is generated by applying a gate voltage with a different final magnitude, wherein a plurality of circuit segments are connected in parallel between the drain region of the memory cell and a drain voltage generator, each circuit segment comprising a resistor connected in series with a transistor having a control gate, whereby selectively applying a control voltage the control gate of to at least one transistor adjusts a voltage applied to the drain region of the memory cell.

9. The method of claim 1 , wherein the drain-to-source bias voltage is selected to maintain a drain current having a substantially constant magnitude.

10. The method of claim 1 , wherein a reverse back bias is applied between the substrate and the control gate.

11. A method of selecting a threshold voltage corresponding to one of at least three programming states of a memory cell of an electrically erasable programmable read only memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the method comprising:

generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region; and

generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, the gate voltage being ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the gate voltage ramped with a ramping rate, whereby the selected threshold voltage for each programming state is generated by applying a gate voltage with a different final magnitude, wherein the ramping rate is between approximately 5.5 V/ms and approximately 10.5 V/ms.

12. The method of claim 11 , wherein the final magnitude is between approximately 5.5 V and approximately 10.5 V.

13. The method of claim 11 , wherein the drain-to-source bias voltage is substantially constant.

14. The method of claim 11 , wherein the drain-to-source bias voltage comprises at least one voltage pulse having a period.

15. The method of claim 14 , wherein the period is between approximately 1 nanosecond and approximately 10 microseconds.

16. The method of claim 11 , wherein the drain-to-source bias voltage is approximately 5 volts.