Memory device and method having data path with multiple prefetch I/O configurations
View Patent ↗A memory device is operable in either a high mode or a low speed mode. In either mode 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
1. A data path for coupling data between a memory array and a plurality of data bus terminals, the data path comprising:
M*N flip-flops coupled to the memory array to receive respective read data bits from the memory array;
an M*N-bit data bus coupled to the M*N flip-flops;
a first set of N parallel-to-serial converters coupled to the M*N-bit data bus, each of the parallel-to-serial converters in the first set being operable to receive either M or M/2 parallel data bits from the M*N flip-flops, to convert the M or M/2, respectively, parallel data bits to M or M/2, respectively, serial data bits, and to couple the M or M/2, respectively, serial data bits to a respective one of N data bus terminals;
a second set of N parallel-to-serial converters coupled to the M*N-bit data bus, each of the parallel-to-serial converters in the second set being operable to receive M/2 parallel data bits from the flip-flops, to convert the M/2 parallel data bits to M/2 serial data bits, and to couple the M/2 serial data bits to a respective one of N data bus terminals; and
a control circuit operable in a first operating mode to cause M*N bits of data from the M*N flip-flops to be coupled through the M*N-bit bus in parallel and to cause M of the parallel data bits to be coupled to each of the N parallel-to-serial converters in the first set, and being operable in a second operating mode to cause M*N bits of data from the M*N flip-flops to be coupled through the M*N-bit bus in parallel and to cause M/2 of the parallel data bits to be coupled to each of the N parallel-to-serial converters in the first set and to each of the N parallel-to-serial converters in the second set.
2. The data path of claim 1 wherein M is equal to 8 and N is equal to 8.
3. The data path of claim 1 wherein the memory array comprises first and second sub-arrays, and wherein the M*N flip-flops comprise a first set of M*N/2 flip-flops coupled to the first sub-array and a second set of M*N/2 flip-flops coupled to the second sub-array.