DRAM power bus control
View Patent ↗A dynamic random access memory (DRAM) is provided that has separate array and peripheral power busing to isolate array noise from peripheral circuits such as delay lock loops during row activations and read/write memory operations. A switch connects the array power bus to another separate power bus for a limited period of time during a DRAM refresh cycle to provide additional current to the DRAM arrays. The switch disconnects the array power bus from the other power bus preferably before the end of the refresh cycle.
1. A method of controlling power distribution on an integrated circuit chip having dynamic random access memory, said dynamic random access memory comprising at least one array operative to be read from and written to and being periodically refreshed in order to maintain stored values, said method comprising:
powering a delay lock loop circuit with a first power bus and a first ground bus;
powering reads and writes of said array with a second power bus and a second ground bus, said second power bus not coupled to said first power bus and said second ground bus not coupled to said first ground bus; and
coupling said second power bus to a third power bus for a finite period of time during said periodic refreshing of said array.
2. The method of claim 1 further comprising:
coupling said first power bus to a first integrated circuit chip power pad; and
coupling said second power bus to a second integrated circuit chip power pad.
3. The method of claim 2 further comprising:
regulating voltage on said first power bus; and
regulating voltage on said second power bus.
4. The method of claim 2 wherein said third power bus has a higher voltage than said second power bus.
5. The method of claim 2 further comprising coupling said third power bus to said first integrated circuit chip power pad.
6. The method of claim 5 wherein said voltage on said third power bus is unregulated.
7. The method of claim 1 wherein said coupling comprises coupling said second power bus to an unregulated third power bus for a finite period of time during said periodic refreshing of said array.
8. The method of claim 1 further comprising before said coupling:
refreshing said dynamic random access memory in order to maintain stored values; and
after said coupling:
de-coupling said second power bus from said third power bus prior to completion of said refreshing.