Non-volatile memory structure
View Patent ↗A non-volatile memory cell utilizes a programmable conductor random access memory (PCRAM) structure instead of a polysilicon layer for a floating gate. Instead of storing or removing electrons from a floating gate, the programmable conductor is switched between its low and high resistive states to operate the flash memory cell. The resulting cell can be erased faster and has better endurance than a conventional flash memory cell.
1. A memory cell, comprising:
a substrate, said substrate including a source region and a drain region;
a first insulating layer over said substrate;
a first conductive layer over said first insulating layer and between said source and drain regions:
a programmable conductance element over said first conductive layer, said programmable conductance element having a resistance which is controllable between at least two states; and
a second conductive layer over said programmable conductance element.
2. The memory cell of claim 1 , wherein said programmable conductance element is comprised of a chalcogenide glass.
3. The memory cell of claim 2 , wherein said chacogenide glass is comprised of germanium-selenide.
4. The memory cell of claim 2 , wherein said chacogenide glass comprises Ge x Se 100-x .
5. The memory cell of claim 4 , wherein x has a range of from 18 to 43.
6. The memory cell of claim 5 , wherein x is 20.
7. The memory cell of claim 2 , wherein said chacogenide glass is doped with metal.
8. The memory cell of claim 2 , wherein said chacogenide glass is doped with silver.
9. The memory cell of claim 1 , wherein said first and second conductive layers are comprised of one of tungsten, nickel, tantalium, aluminum, platinum, and silver.
10. A memory device, comprising:
a control circuit;
a memory array, coupled to said control circuit, said memory array further comprising a plurality of blocks, each of said plurality of blocks including a plurality of memory cells,
wherein each of said memory cells comprises, a substrate, the substrate having a source region and a drain region;
a first insulating layer over said substrate;
a first conductive layer over said first insulating layer and between said source and drain regions:
a programmable conductance element over said first conductive layer, said programmable conductance element having a resistance which is controllable between two states; and
a second conducive layer over said programmable conductance element.
11. The device of claim 10 , wherein said programmable conductance element is comprised of a chalcogenide glass.
12. The device of claim 11 , wherein said chacogenide glass is comprised of germanium-selenide.
13. The device of claim 11 , wherein said chacogenide glass is comprised of Ge x Se 100-x .
14. The device of claim 13 , wherein x has a range of 18 to 43.
15. The device of claim 14 , wherein x is 20.
16. The device of claim 10 , wherein said chacogenide glass is doped with a metal.
17. The device of claim 10 , wherein said chacogenide glass is doped with silver.
18. The device of claim 10 , wherein said first and second conductive layers are comprised of one of tungsten, nickel, tantalium, aluminum, platinum, and silver.
19. A processor based system, comprising:
a processor;
a memory device, said memory device including a plurality of memory cells, wherein each of said memory cells comprises,
a substrate, the substrate having a source region and a drain region;
a first insulating layer over said substrate;
a first conductive layer over said first insulating layer and between said source and drain regions:
a programmable conductance element over said first conductive layer, said programmable conductance element having a resistance which is controllable between two states; and
a second conductive layer over said programmable conductance element.
20. The device of claim 19 , wherein said programmable conductance element is comprised of a chalcogenide glass.
21. The device of claim 20 , wherein said chacogenide glass is comprised of germanium-selenide.
22. The device of claim 20 , wherein said chacogenide glass has a chemical formula of Ge x Se 100-x .
23. The device of claim 22 , wherein x has a range of 18 to 43.
24. The device of claim 23 , wherein x is 20.
25. The device of claim 20 , wherein said chacogenide glass is doped with a metal.
26. The device of claim 20 , wherein said chacogenide glass is doped with silver.
27. The device of claim 19 , wherein said first and second conductive layers are comprised of one of tungsten, nickel, tantalium, aluminum, platinum, and silver.
28. The memory cell of claim 1 , wherein said programmable conductance element is a multi-layer structure comprised of:
a first layer comprising Ge 40 Se 60 ;
a second layer, formed over said first layer, said second layer comprising,
at least one of,
a sublayer of Ag, and
a sublayer of Ag 2 Se;
a third layer, formed over said second layer, comprised of Ge 40 Se 60 ;
a fourth layer, formed over said third layer, comprising Ag; and
a fifth layer, formed over said fourth layer, comprising Ge 40 Se 60 .
29. The memory cell of claim 10 , wherein said programmable conductance element is a multi-layer structure comprised of:
a first layer comprising Ge 40 Se 60 ;
a second layer, formed over said first layer, said second layer comprising,
at least one of,
a sublayer of Ag, and
a sublayer of Ag 2 Se;
a third layer, formed over said second layer, comprised of Ge 40 Se 60 ;
a fourth layer, formed over said third layer, comprising Ag; and
a fifth layer, formed over said fourth layer, comprising Ge 40 Se 60 .
30. The system of claim 19 , wherein said programmable conductance element is a multi-layer structure comprised of:
a first layer comprising Ge 40 Se 60 ;
a second layer, formed over said first layer, said second layer comprising,
at least one of,
a sublayer of Ag, and
a sublayer of Ag 2 Se;
a third layer, formed of said second layer, comprised of Ge 40 Se 60 ;
a fourth layer, formed over said third layer, comprising Ag; and
a fifth layer, formed over said fourth layer, comprising Ge 40 Se 60 .