IP Library Granted Patent US 7,239,029
Granted Patent B2
US 7,239,029 · App. 10/340,331 · Granted Jul 3, 2007

Packages for semiconductor die

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Quick Facts
Patent No.
US 7,239,029
App. No.
10/340,331
Granted
Jul 3, 2007
Kind
B2
Abstract

A ball grid array assembly includes a package cover that encapsulates a die and a portion of a substrate to which the die is attached, including an edge of the substrate. Encapsulation of the substrate edge by the cover reduces penetration of moisture or other contaminants into the substrate. The cover includes a rib that extends to contact a circuit board to which the ball grid array assembly is connected. With such a rib, planarity between the circuit board and the substrate is maintained during soldering.

Claims (11)

1. An assembly, comprising:

a substrate having a first major surface, a second major surface opposed to the first major surface, and a substrate edge extending between the first and second major surfaces and defining a circuit pattern configured to electrically connect the first major surface and the second major surface;

a plurality of semiconductor die mounted to the first major surface of the substrate and electrically connected to the pattern; and

a package cover situated to encapsulate at least a portion of each semiconductor die, the first major surface, the second major surface, and the substrate edge, wherein the package-cover extends from the first major surface over a portion of the substrate edge to at least a portion of the second major surface.

2. The assembly of claim 1 , wherein the package cover is configured to encapsulate at least a portion of the second major surface.

3. An assembly, comprising:

a substrate having a first major surface, a second major surface opposed to the first major surface, and a substrate edge extending between the first and second major surfaces;

a plurality of semiconductor die mounted to the first major surface of the substrate and electrically connected to the substrate;

a package cover comprised of a material, the package cover situated to encapsulate at least a portion of each semiconductor die and the first major surface;

a plurality of solder balls connected to the second major surface; and

at least one rib that is coupled to and extends outwardly away from the second major surface, wherein the at least one rib is comprised of the material of the package cover, and wherein at least some portion of the substrate edge is not covered by the package cover or the at least one rib.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2010
From: MICRON TECHNOLOGY, INC.
To: ROUND ROCK RESEARCH, LLC
Reel/Frame 023786/0416 →