Capacitor structures, DRAM cell structures, and integrated circuitry, and methods of forming capacitor structures, integrated circuitry and DRAM cell structures
View Patent ↗The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.
1. A semiconductor construction, comprising:
an insulative layer over a semiconductive substrate and having an uppermost surface, an opening extending at least partially into the insulative layer; a periphery of the opening comprising sidewalls of the insulative layer, the sidewalls intersecting the uppermost surface to define corners;
a conductive masking layer over portions of the sidewalls and narrowing a lateral width of the opening; the conductive masking layer extending from the sidewalls, over the corners, and over a portion of the uppermost surface of the insulative layer;
a storage electrode layer against the conductive masking layer and extending at least partially into the opening;
a dielectric layer proximate the storage electrode layer; and
a cell electrode layer proximate the dielectric layer.
2. The semiconductor construction of claim 1 wherein the storage electrode layer comprises doped polysilicon and wherein the conductive masking layer comprises doped polysilicon.
3. The semiconductor construction of claim 1 wherein the storage electrode layer comprises a roughened silicon-containing upper surface.
4. The semiconductor construction of claim 1 wherein the conductive masking layer comprises a single layer.