Conductive container structures having a dielectric cap
View Patent ↗Container structures for use in integrated circuits and methods of their manufacture. The container structures have a dielectric cap on the top of a conductive container to reduce the risk of container-to-container shorting by insulating against bridging of conductive debris across the tops of adjacent container structures. The container structures are adapted for use in memory cells and apparatus incorporating such memory cells, as well as other integrated circuits.
1. A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
forming an insulating layer on the substrate;
forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer;
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer, wherein the fill layer fills the opening; and
removing the conductive layer and the fill layer to a level below a top of the insulating layer;
wherein the bottom plate has a cylindrical shape, the bottom plate includes at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon, and the silicon material is conductively doped;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a dielectric layer on the insulating layer, the conductive layer and the fill layer; and
removing the dielectric layer from the insulating layer and the fill layer, wherein the dielectric cap includes at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides, and wherein the dielectric cap is annealed at approximately 600 degree C. to 1000 degree C. for approximately 10 to 20 seconds;
a dielectric layer on the bottom plate and the dielectric cap, wherein the dielectric cap is adapted to form part of the dielectric layer; and
a cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate.
2. The semiconductor die of claim 1 , wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon.
3. The semiconductor die of claim 1 , wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides.
4. The semiconductor die of claim 1 , wherein the dielectric cap is annealed.
5. The semiconductor die of claim 1 , wherein the bottom plate has a cylindrical shape.
6. The semiconductor die of claim 1 , wherein the dielectric cap is adapted to form part of the dielectric layer.
7. A semiconductor die, comprising:
an integrated circuit supported by a substrate and having a plurality of integrated circuit devices, wherein at least one of the plurality of integrated circuit devices is a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
forming an insulating layer on the substrate;
forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer;
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer, wherein the fill layer fills the opening;
removing the fill layer to a level substantially even with a top of the insulating layer; and
removing the conductive layer to a level below the level below the top of the insulating layer,
wherein the bottom plate has a cylindrical shape, the bottom plate includes at least one silicon material selected from the group consisting essentially of amorphous silicon, polysilicon and hemispherical grain polysilicon, and the silicon material is conductively doped;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a dielectric layer on the insulating layer, the conductive layer and the fill layer; and
removing the dielectric layer from the insulating layer and the fill layer,
wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides, and wherein the dielectric cap is annealed at approximately 600 degree C. to 1000 degree C. for approximately 10 to 20 seconds;
a dielectric layer on the bottom plate and the dielectric cap, wherein the dielectric cap is adapted to form part of the dielectric layer; and
a cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate.
8. A memory device, comprising:
an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
forming an insulating layer on a substrate;
forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer;
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer, wherein the fill layer fills the opening; and
removing the conductive layer and the fill layer to a level below a top of the insulating layer;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a dielectric layer on the insulating layer, the conductive layer and the fill layer; and
removing the dielectric layer from the insulating layer and the fill layer;
a dielectric layer on the bottom plate and the dielectric cap; and
a cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit.
9. The memory device of claim 8 , wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon.
10. The memory device of claim 8 , wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides.
11. The memory device of claim 8 , wherein the dielectric cap is annealed.
12. The memory device of claim 8 , wherein the bottom plate has a substantially cylindrical shape.
13. The memory device of claim 8 , wherein the dielectric cap is adapted to form part of the dielectric layer.
14. The memory device of claim 9 , wherein the silicon material is conductively doped.
15. The memory device of claim 11 , wherein the dielectric cap is annealed at approximately 600 degree C. to 1000 degree C. for approximately 10 to 20 seconds.
16. A memory device, comprising:
an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
forming an insulating layer on a substrate;
forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer;
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer, wherein the fill layer fills the opening; and
removing the conductive layer and the fill layer to a level below a top of the insulating layer;
wherein the bottom plate has a cylindrical shape, the bottom plate includes at least one silicon material selected from the group consisting essentially of amorphous silicon, polysilicon and hemispherical grain polysilicon, and the silicon material is conductively doped;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a dielectric layer on the insulating layer, the conductive layer and the fill layer; and
removing the dielectric layer from the insulating layer and the fill layer,
wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides, and wherein the dielectric cap is annealed at approximately 600 degree C. to 1000 degree C. for approximately 10 to 20 seconds;
a dielectric layer on the bottom plate and the dielectric cap, wherein the dielectric cap is adapted to form part of the dielectric layer;
a cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit.
17. A memory device, comprising:
an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
forming an insulating layer on a substrate;
forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer;
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer, wherein the fill layer fills the opening;
removing the fill layer to a level substantially even with a top of the insulating layer; and
removing the conductive layer to a level below the level below the top of the insulating layer;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a dielectric layer on the insulating layer, the conductive layer and the fill layer; and
removing the dielectric layer from the insulating layer and the fill layer;
a dielectric layer on the bottom plate and the dielectric cap; and
a cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and
an address decoder circuit coupled to the row access circuit and the column access circuit.
18. The memory device of claim 17 , wherein the bottom plate comprises at least one silicon material selected from the group consisting of amorphous silicon, polysilicon and hemispherical grain polysilicon.
19. The memory device of claim 17 , wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides.
20. The memory device of claim 17 , wherein the dielectric cap is annealed.
21. The memory device of claim 17 , wherein the bottom plate has a substantially cylindrical shape.
22. The memory device of claim 17 , wherein the dielectric cap is adapted to form part of the dielectric layer.
23. The memory device of claim 18 , wherein the silicon material is conductively doped.
24. The memory device of claim 20 , wherein the dielectric cap is annealed at 600 degree C. to 1000 degree C. for approximately 10 to 20 seconds.
25. A memory device, comprising:
an array of memory cells, wherein at least one memory cell has a container capacitor, the container capacitor comprising:
a bottom plate having a closed bottom and sidewalls extending upward from the closed bottom, wherein the bottom plate is formed by a method comprising:
forming an insulating layer on a substrate;
forming an opening in the insulating layer, wherein the opening has a bottom on an exposed portion of the substrate and sidewalls defined by the insulating layer;
forming a conductive layer on the insulating layer and the exposed portion of the substrate;
forming a fill layer on the conductive layer, wherein the fill layer fills the opening;
removing the fill layer to a level substantially even with a top of the insulating layer; and
removing the conductive layer to a level below the level below the top of the insulating layer,
wherein the bottom plate has a cylindrical shape, the bottom plate includes at least one silicon material selected from the group consisting essentially of amorphous silicon, polysilicon and hemispherical grain polysilicon, and the silicon material is conductively doped;
a dielectric cap on a top of the sidewalls, wherein the dielectric cap is formed by a method comprising:
forming a dielectric layer on the insulating layer, the
conductive layer and the fill layer; and
removing the dielectric layer from the insulating layer and the fill layer,
wherein the dielectric cap comprises at least one dielectric material selected from the group consisting of oxides, nitrides and silicon oxynitrides, and wherein the dielectric cap is annealed at approximately 600 degree C. to 1000 degree C. for approximately 10 to 20 seconds;
a dielectric layer on the bottom plate and the dielectric cap, wherein the
dielectric cap is adapted to form part of the dielectric layer;
a cell plate on the dielectric layer, wherein the dielectric layer is interposed between the cell plate and the bottom plate;
a row access circuit coupled to the array of memory cells;
a column access circuit coupled to the array of memory cells; and an address decoder circuit coupled to the row access circuit and the column access circuit.