Memory device and method having data path with multiple prefetch I/O configurations
View Patent ↗A memory device is operable in either a high mode or a low speed mode. In either mode, 32 bits of data from each of two memory arrays are prefetched into respective sets of 32 flip-flops. In the high-speed mode, the prefetched data bits are transferred in parallel to 4 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 4 data bus terminals. In the low speed mode, two sets of prefetched data bits are transferred in parallel to 8 parallel-to-serial converters, which transform the parallel data bits to a burst of 8 serial data bits and apply the burst to a respective one of 8 data bus terminals.
1. A method of transferring data from a memory device in either a first operating mode or a second operating mode, the method comprising:
in the first operating mode:
transferring the data from the memory device to each of N parallel-to-serial converters in the form of one set of M-bit parallel data so that N×M bits of parallel data are collectively transferred from the memory device to the N parallel-to-serial converters;
transferring the data from each of the N parallel-to-serial converters in the form of M bits of data output in sequence from each of the N parallel-to-serial converters so that M sets of N-bit parallel data are output from the N parallel-to-serial converters; and
in the second operating mode:
transferring the data from the memory device to each of 2N parallel-to-serial converters in the form of two sets of M/2-bit parallel data each so that a first set of N×M bits of parallel data are collectively transferred from the memory device to the 2N parallel-to-serial converters and a second set of N×M bits of parallel data are subsequently collectively transferred from the memory device to the 2N parallel-to-serial converters; and
transferring the write data from each of the 2N parallel-to-serial converters in the form of M bits of data output in sequence from each of the 2N parallel-to-serial converters so that M sets of 2N-bit parallel data are output from the 2N parallel-to-serial converters.
2. The method of claim 1 wherein N is equal to 8 and M is equal to 8.
3. The method of claim 1 wherein the act of transferring the data from the memory device to the N parallel-to-serial converters in the first operating mode comprises executing a memory read operation, and wherein the act of transferring the data from the memory device to each of the 2N parallel-to-serial converters in the second operating mode comprises sequentially executing two memory read operations.
4. The method of claim 1 wherein the memory device comprises a dynamic random access memory device.
5. The method of claim 1 wherein the parallel-to-serial converters are integrally fabricated with the memory device.