Semiconductor memory circuitry including die sites sized for 256M to 275M memory cells in an 8-inch wafer
View Patent ↗Processes are disclosed which facilitate improved high-density memory circuitry, most preferably dynamic random access memory (DRAM) circuitry. In accordance with aspects of the invention, considerably greater numbers of die sites per wafer are achieved for 6-inch, 8-inch and 12-inch wafers for 4M, 16M, 64M and 256M integration levels. Further, a semiconductor memory device includes i) a plurality of functional and operably addressable memory cells arranged in multiple memory arrays formed on a semiconductor die; and ii) circuitry formed on the semiconductor die permitting data to be written to and read from one or more of the memory cells, at least one of the memory arrays containing at least 100 square microns of continuous die surface area having at least 170 of the functional and operably addressable memory cells.
1. A plurality of 256M semiconductor memory devices comprising:
a processed semiconductor wafer ready for dicing having a major diameter of about 8 inches; and
a plurality of die sites on the processed wafer, the die sites being sized for respective receipt of at least 256,000,000 functional and operably addressable memory cells arranged in multiple memory arrays within a respective die site, a predominant number of a total number of die sites on the processed wafer being occupied by memory devices having at least 256,000,000 functional and operably addressable memory cells arranged in multiple memory arrays within a respective die site, the total number of die sites on the processed wafer being at least 86.
2. The plurality of 256M semiconductor memory devices of claim 1 wherein the total number of die sites on the processed wafer is at least 89.