Methods of forming memory cells and arrays having underlying source-line connections
View Patent ↗Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed at regular intervals across a memory array. Such floating-gate memory cells have their drain regions and source regions formed in a first semiconductor region having a first conductivity type. This first semiconductor region is separated from the underlying substrate by an interposing second semiconductor region having a second conductivity type different from the first conductivity type. The source regions of the memory cells are coupled to the second semiconductor region as a common source line. Such memory cells can be programmed, read and erased by applying various potential levels to their control gates, their drain regions, the first semiconductor region, and the second semiconductor region.
1. A method of forming a memory cell, comprising:
forming a gate stack on a first semiconductor region having a first conductivity type, wherein the first semiconductor region is enclosed in a second semiconductor region having a second conductivity type different from the first conductivity type;
forming first and second source/drain regions on opposing sides of the gate stack, wherein the source/drain regions have the second conductivity type; and
forming a source-line contact, wherein the source-line contact is directly coupled between the first source/drain region and the second semiconductor region and the second source/drain region is not coupled to the second semiconductor region.
2. The method of claim 1 , wherein the method is performed in the order presented.
3. A method of forming a memory array, comprising:
forming a plurality of gate stacks on a first semiconductor region having a first conductivity type, wherein the first semiconductor region is enclosed in a second semiconductor region having a second conductivity type different from the first conductivity type;
forming source regions in the first semiconductor region and on a first side of each gate stack, wherein the source regions have the second conductivity type;
forming drain regions in the first semiconductor region and on a second side of each gate stack, wherein the drain regions have the second conductivity type; and
forming a plurality of source-line contacts, wherein each source-line contact is directly coupled between the second semiconductor region and at least one source region, wherein the drain regions are not coupled to the second semiconductor region or source-line contacts.
4. The method of claim 3 , further comprising forming a plurality of conductive traces, wherein each conductive trace couples at least one source region to a source-line contact.
5. The method of claim 3 , wherein each source-line contact is coupled between the second semiconductor region and only one source region.
6. The method of claim 3 , wherein each source-line contact extends through at least one source region.
7. The method of claim 3 , wherein the method is performed in the order presented.
8. A method of forming a memory array, comprising:
forming a plurality of gate stacks on a p-well, wherein the p-well is isolated from a p-type substrate by an n-well;
forming n + -type source regions in the p-well and on a first side of each gate stack;
forming n + -type drain regions in the p-well and on a second side of each gate stack; and
forming a plurality of source-line contacts, wherein each source-line contact is directly coupled between the n-well and at least one n + -type source region, wherein the n + -type drain regions are not coupled to the n-well.
9. The method of claim 8 , wherein the method is performed in the order presented.
10. A method of forming a memory array, comprising:
forming a plurality of gate stacks on a p-well, wherein the p-well is isolated from a p-type substrate by an n-well;
forming a plurality of n + -type source regions in the p-well and on a first side of each gate stack;
forming a plurality of n + -type drain regions in the p-well and on a second side of each gate stack; and
forming a plurality of source-line contacts, wherein each source-line contact extends through at least one n + -type source region to the n-well, wherein the n + -type drain regions are not connected to the n-well.
11. The method of claim 10 , wherein the method is performed in the order presented.