Programming methods for multi-level memory devices
View Patent ↗A method is provided for programming a memory cell. The memory cell is fabricated on a substrate and comprises a source region, a drain region, a floating gate, and a control gate. The memory cell has a threshold voltage selectively configurable into one of at least three programming states. The method includes generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region. The method further includes injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate. A selected threshold voltage for the memory cell corresponding to a selected one of the programming states is generated by applying a different selected gate voltage.
1. A method for selecting a threshold voltage corresponding to one of at least three programming states of a memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the method comprising:
generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region, the drain-to-source bias voltage comprising at least one voltage pulse; and
generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, whereby the selected threshold voltage for each programming state is generated by applying a different selected gate voltage, wherein a transistor comprising a control gate is connected in series between the drain region of the memory cell and a drain voltage generator, whereby a control voltage applied to the control gate of the transistor adjusts a voltage applied to the drain region of the memory cell.
2. A method for selecting a threshold voltage corresponding to one of at least three programming states of a memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the method comprising:
generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region, the drain-to-source bias voltage comprising at least one voltage pulse; and
generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, whereby the selected threshold voltage for each programming state is generated by applying a different selected gate voltage, wherein a plurality of circuit segments are connected in parallel between the drain region of the memory cell and a drain voltage generator, each circuit segment comprising a resistor connected in series with a transistor having a control gate, whereby selectively applying a control voltage to the control gate of at least one transistor adjusts a voltage applied to the drain region of the memory cell.
3. A method for selecting a threshold voltage corresponding to one of at least three programming states of a memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the method comprising:
generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region, the drain-to-source bias voltage comprising at least one voltage pulse; and
generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, whereby the selected threshold voltage for each programming state is generated by applying a different selected gate voltage for a selected period of time, wherein the selected period of time is between approximately 1 nanosecond and approximately 10 microseconds.
4. A method for selecting a threshold voltage corresponding to one of at least three programming states of a memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the method comprising:
generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region, the drain-to-source bias voltage comprising at least one voltage pulse; and
generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, whereby the selected threshold voltage for each programming state is generated by applying a different selected gate voltage, wherein the selected gate voltage is ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the selected gate voltage being ramped with a ramping rate of from between approximately 5.5 V/ms and approximately 10.5 V/ms.
5. A method for selecting a threshold voltage corresponding to one of at least three programming states of a memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the method comprising:
generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region, the drain-to-source bias voltage comprising at least one voltage pulse; and
generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, whereby the selected threshold voltage for each programming state is generated by applying a different selected gate voltage, wherein the selected gate voltage is ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the selected gate voltage being ramped with a ramping rate, wherein the final magnitude is between approximately 5.5 V and approximately 10.5 V.
6. A method for selecting a threshold voltage corresponding to one of at least three programming states of a memory, the memory cell fabricated on a substrate and comprising a source region, a drain region, a floating gate, and a control gate, the method comprising:
generating a drain current between the drain region and the source region by applying a drain-to-source bias voltage between the drain region and the source region, the drain-to-source bias voltage comprising at least one voltage pulse; and
generating a selected threshold voltage for the memory cell corresponding to a selected one of the programming states by injecting hot electrons from the drain current to the floating gate by applying a gate voltage to the control gate, whereby the selected threshold voltage for each programming state is generated by applying a different selected gate voltage, wherein the voltage pulse of the drain-to-source bias voltage has a period of between approximately 1 nanosecond and approximately 10 microseconds.
7. The method of claim 1 , wherein the selected gate voltage is applied for a selected period of time.
8. The method of claim 1 , wherein the selected gate voltage is ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the selected gate voltage being ramped with a ramping rate.
9. The method of claim 1 , wherein a reverse back bias is applied between the substrate and the control gate.
10. The method of claim 2 , wherein the selected gate voltage is applied for a selected period of time.
11. The method of claim 2 , wherein the selected gate voltage is ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the selected gate voltage being ramped with a ramping rate.
12. The method of claim 2 , wherein a reverse back bias is applied between the substrate and the control gate.
13. The method of claim 3 , wherein the voltage pulse of the drain-to-source bias voltage is applied while the selected gate voltage is applied.
14. The method of claim 3 , wherein the selected gate voltage is ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the selected gate voltage being ramped with a ramping rate.
15. The method of claim 3 , wherein a reverse back bias is applied between the substrate and the control gate.
16. The method of claim 4 , wherein the selected gate voltage is applied for a selected period of time.
17. The method of claim 4 , wherein the voltage pulse of the drain-to-source bias voltage is applied while the selected gate voltage is applied.
18. The method of claim 4 , wherein a reverse back bias is applied between the substrate and the control gate.
19. The method of claim 5 , wherein the selected gate voltage is applied for a selected period of time.
20. The method of claim 5 , wherein the voltage pulse of the drain-to-source bias voltage is applied while the selected gate voltage is applied.
21. The method of claim 5 , wherein a reverse back bias is applied between the substrate and the control gate.
22. The method of claim 6 , wherein the selected gate voltage is ramped from an initial magnitude to a final magnitude greater than the initial magnitude, the selected gate voltage being ramped with a ramping rate.
23. The method of claim 6 , wherein the ramping rate is between approximately 5.5 V/ms and approximately 10.5 V/ms.
24. The method of claim 6 , wherein a reverse back bias is applied between the substrate and the control gate.