Semiconductor device having recess and planarized layers
View Patent ↗A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.
1. A semiconductor device comprising:
an isolation layer having a surface and a recess;
a first conductive layer in the recess having an endpoint defined by the surface and a second surface in the recess;
an electrically insulating layer having a first portion in the recess on the second surface and a second portion on the surface; and
a second conductive layer on the insulating layer.
2. The semiconductor device of claim 1 wherein the second surface of the first conductive layer comprises a roughened surface.
3. The semiconductor device of claim 1 wherein the first conductive layer is configured for capacitive coupling with the second conductive layer.
4. The semiconductor device of claim 1 wherein the first conductive layer comprises hemispherical grain polysilicon.
5. The semiconductor device of claim 1 wherein the semiconductor device comprises a flash EEPROM.
6. The semiconductor device of claim 1 wherein the semiconductor device comprises a transistor.
7. The semiconductor device of claim 1 wherein the first conductive layer comprises a floating gate.
8. The semiconductor device of claim 1 wherein the insulating layer comprises an oxide.
9. The semiconductor device of claim 1 wherein the isolation layer comprises an oxide.
10. A semiconductor device comprising:
an isolation layer having a surface and a recess with an inner periphery;
a first conductive layer in the recess having a self aligned peripheral shape defined by the inner periphery, a second surface in the recess and an endpoint defined by the surface;
an electrically insulating layer having a first portion in the recess on the second surface and a second portion on the surface; and
a second conductive layer on the insulating layer capacitively coupled to the first conductive layer.
11. The semiconductor device of claim 10 wherein the surface and the endpoint comprise planarized surfaces.
12. The semiconductor device of claim 10 wherein the second surface of the first conductive layer comprises a concave surface.
13. A semiconductor device comprising:
a substrate;
an isolation layer on the substrate having a surface and a recess;
a first conductive layer and a second conductive layer at least partially in the recess separated by an electrically insulating layer;
the first conductive layer having an endpoint defined by the surface and a second surface in the recess;
the insulating layer having a first portion on the second surface and a second portion on the surface.
14. The semiconductor device of claim 13 wherein the substrate comprises silicon.
15. The semiconductor device of claim 13 wherein the first conductive layer comprises a floating gate.
16. The semiconductor device of claim 13 wherein the insulating layer comprises an oxide.
17. The semiconductor device of claim 13 wherein the isolation layer comprises an oxide.