IP Library Granted Patent US 8,456,007
Granted Patent B2
US 8,456,007 · App. 12/249,774 · Granted Jun 4, 2013

Chemical vapor deposition of titanium

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Quick Facts
Patent No.
US 8,456,007
App. No.
12/249,774
Granted
Jun 4, 2013
Kind
B2
Abstract

A titanium layer is formed on a substrate with chemical vapor deposition (CVD). First, a seed layer is formed on the substrate by combining a first precursor with a reducing agent by CVD. Then, the titanium layer is formed on the substrate by combining a second precursor with the seed layer by CVD. The titanium layer is used to form contacts to active areas of substrate and for the formation of interlevel vias.

Claims (15)

1. A memory device, comprising: a memory array; a control circuit operatively coupled to the memory array; and an input/output circuit operatively coupled to the memory array, wherein at least one of the memory array, the control circuit, or the input/output circuit further comprises a via having:

a layer of a titanium alloy formed to overlay walls of a contact hole, wherein the titanium alloy comprises titanium and an element selected from the group consisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic and antimony,

a titanium silicide contact formed in the layer of titanium alloy and having a composition that is different than the layer of titanium alloy, the titanium silicide contact being directly coupled to the layer of titanium alloy, and a fill coupled to the layer of titanium alloy, the fill comprising a metal selected from the group consisting of tungsten and aluminum.

2. The memory of claim 1 , wherein the titanium has an atomic percentage of from about 50% to about 90% of the titanium alloy.

3. The memory of claim 1 , wherein the fill has a level approximately equal to a height of the via.

4. A memory device, comprising: a memory array; a control circuit operatively coupled to the memory array; and an input/output circuit operatively coupled to the memory array, wherein at least one of the memory array, the control circuit, or the input/output circuit comprises:

a layer of a titanium alloy formed to overlay walls of a contact hole, wherein the titanium alloy comprises titanium and an element selected from the group consisting of zinc, cadmium, mercury, aluminum, gallium, indium, tin, silicon, germanium, lead, arsenic and antimony; and

a titanium silicide contact formed in the layer of titanium alloy and having a composition that is different than the layer of titanium alloy, the titanium silicide contact being directly coupled to the layer of titanium alloy and produced using a method comprising:

forming a seed layer within the contact opening by combining a first precursor with a first reducing agent, and;

forming the titanium alloy layer within the contact opening by combining a titanium-containing precursor with the seed layer to form a titanium alloy layer having at least 100% step coverage within the contact.

5. The memory of claim 4 , wherein the titanium has an atomic percentage of from about 50% to about 90% of the titanium alloy.

6. The memory of claim 4 , further comprising:

a contact hole conductive plug formed from selective deposition of a conductive material selected from the list including tungsten and aluminum.

7. The memory of claim 6 , further comprising:

a titanium nitride layer disposed underneath the contact hole conductive plug and above the titanium silicide.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2010
From: MICRON TECHNOLOGY, INC.
To: ROUND ROCK RESEARCH, LLC
Reel/Frame 023786/0416 →