CMOS imager with selectively silicided gate

1. A CMOS imager having improved transistor speed comprising:

a substrate doped to a first conductivity type;

an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed; and

signal processing circuitry on said substrate, wherein said circuitry is connected to said array.

2. The CMOS imager according to claim 1 , wherein said opaque conductive layer is an opaque conductive suicide layer.

3. The CMOS imager according to claim 2 , wherein said opaque conductive suicide layer is a tungsten silicide.

4. The CMOS imager according to claim 2 , wherein said opaque conductive silicide layer is a titanium suicide.

5. The CMOS imager according to claim 2 , wherein said opaque conductive suicide layer is a cobalt silicide.

6. The CMOS imager according to claim 2 , wherein said opaque conductive suicide layer is a molybdenum suicide.

7. The CMOS imager according to claim 2 , wherein said opaque conductive layer is an opaque conductive barrier metal layer.

8. The CMOS imager according to claim 7 , wherein said opaque conductive barrier metal layer is a TiN/W layer.

9. The CMOS imager according to claim 7 , wherein said opaque conductive barrier metal layer is a WN x /W layer.

10. The CMOS imager according to claim 7 , wherein said opaque conductive barrier metal layer is a WN x layer.

11. The CMOS imager according to claim 1 , wherein said transistor is one or more of a reset transistor, a row select transistor, source follower transistor, amplifier transistor or a transfer transistor.

12. The CMOS imager according to claim 1 , wherein said transistor is a reset transistor.

13. The CMOS imager according to claim 12 , further comprising a transfer transistor to transfer charge from said photocollection region to said signal processing circuitry, wherein said transfer transistor includes an opaque conductive layer deposited over the gate region of said transistor.

14. The CMOS imager according to claim 1 , wherein said imager further includes a thin ring of opaque conductive layer formed over the outer periphery of said photogate.

15. The CMOS imager according to claim 14 , wherein said imager further includes a light shield formed over said imager such that said light shield does not cover a substantial portion of said photocollection region.

16. A processing system comprising:

(i) a processor; and

(ii) a CMOS imaging device coupled to said processor and including:

a substrate doped to a first conductivity type;

an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type, at least one transistor, and a partially removed opaque conductive layer, wherein said transistor includes, over a gate region of the transistor, a remaining portion of said opaque conductive layer, and said photocollection region includes a photogate from which said opaque conductive layer has been removed; and

signal processing circuitry on said substrate, wherein said circuitry is connected to said array.

17. The system according to claim 16 , wherein said opaque conductive layer is an opaque conductive silicide layer.

18. The system according to claim 17 , wherein said opaque conductive suicide layer is a tungsten silicide.

19. The system according to claim 17 , wherein said opaque conductive silicide layer is a titanium silicide.

20. The system according to claim 17 , wherein said opaque conductive suicide layer is a cobalt silicide.

21. The system according to claim 17 , wherein said opaque conductive silicide layer is a molybdenum silicide.

22. The system according to claim 16 , wherein said opaque conductive layer is an opaque conductive barrier metal layer.

23. The system according to claim 22 , wherein said opaque conductive barrier metal layer is a TiN/W layer.

24. The system according to claim 22 , wherein said opaque conductive barrier metal layer is a WN x /W layer.

25. The system according to claim 22 , wherein said opaque conductive barrier metal layer is a WN x layer.

26. The system according to claim 16 , wherein said transistor is one or more of a reset transistor, a row select transistor, an amplifying transistor, a source follower transistor or a transfer transistor.

27. The system according to claim 16 , wherein said transistor is a reset transistor.

28. The system according to claim 27 , further comprising a transfer transistor to transfer charge from said photocollection region to said signal processing circuitry, wherein said transfer transistor includes an opaque conductive layer deposited over the gate region of said transistor.

29. The system according to claim 16 , wherein said imager further includes a thin ring of opaque conductive layer formed over the outer periphery of said photogate.

30. The system according to claim 29 , wherein said imager further includes a light shield formed over said imager such that said light shield does not cover a substantial portion of said photocollection region.

31. A CMOS imager having improved transistor speed comprising:

a substrate doped to a first conductivity type;

an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor; and

signal processing circuitry on said substrate, wherein said circuitry is connected to said array,

wherein said photogate is void of said deposited opaque conductive layer.

32. A processing system comprising:

(i) a processor; and

(ii) a CMOS imaging device coupled to said processor and including:

a substrate doped to a first conductivity type;

an array of pixel cells formed on said substrate, each of said cells including a photocollection region doped to a second conductivity type with an etched photogate, and at least one transistor having a portion of a deposited opaque conductive layer over a gate region of the transistor; and

signal processing circuitry on said substrate, wherein said circuitry is connected to said array,

wherein said photogate is void of said deposited opaque conductive layer.

33. A CMOS imager having improved transistor speed comprising:

a substrate; and

an array of pixel cells formed on said substrate, each of said cells including a photogate, a transfer gate, a reset gate, and a partially removed opaque conductive layer, wherein a remaining portion of said opaque conductive layer remains over said transfer gate and said reset gate, and wherein said photogate is void of said opaque conductive layer.

34. The CMOS imager according to claim 33 , wherein said opaque conductive layer is an opaque conductive silicide layer.

35. The CMOS imager according to claim 34 , wherein said opaque conductive silicide layer is a tungsten silicide.

36. The CMOS imager according to claim 34 , wherein said opaque conductive suicide layer is a titanium suicide.

37. The CMOS imager according to claim 34 , wherein said opaque conductive suicide layer is a cobalt silicide.

38. The CMOS imager according to claim 34 , wherein said opaque conductive silicide layer is a molybdenum silicide.

39. The CMOS imager according to claim 33 , wherein said opaque conductive layer is an opaque conductive barrier metal layer.

40. The CMOS imager according to claim 39 , wherein said opaque conductive barrier metal layer is a TiN/W layer.

41. The CMOS imager according to claim 39 , wherein said opaque conductive barrier metal layer is a WN x /W layer.

42. The CMOS imager according to claim 39 , wherein said opaque conductive barrier metal layer is a WN x layer.