Semiconductor isolator system
View Patent ↗A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.
1. An electrical isolation system for a semiconductor device including a substrate having an active area, the electrical isolation system comprising:
an electrical isolation material contacting the active area of the semiconductor device;
a recess having a wall contacting the electrical isolation material, the recess aligned with at least a portion of the active area; and
a conductive material in the recess having a peripheral shape and an alignment with the active area defined by the recess.
2. The system of claim 1 wherein the conductive material has a generally concave surface configured to provide an increased surface area.
3. The system of claim 1 wherein the electrical isolation material at least partially defines the wall.
4. The system of claim 1 wherein the electrical isolation material comprises an oxide.
5. The system of claim 1 wherein the wall has a sloped surface.
6. An isolator for an active area of a semiconductor device, comprising a first oxide lateral to the active area of the semiconductor device, wherein the first oxide defines at least one sidewall of a recess having a peripheral shape aligned with and substantially enclosing at least a portion of the active area; and a conductive material in the recess having the peripheral shape.
7. The isolator of claim 6 wherein the recess has four sidewalls and the peripheral shape comprises a rectangle.
8. The isolator of claim 6 wherein the conductive material has a generally concave surface within the recess.
9. The isolator of claim 6 wherein the recess contains a second oxide on the active area.
10. The isolator of claim 6 wherein the recess contains a conductive gate on the active area.
11. An electrical isolation system for a semiconductor device including a substrate having a plurality of active areas, the electrical isolation system comprising:
an electrical isolation material on the substrate having a surface;
a plurality of recesses in the electrical isolation material aligned with the active areas, each recess having a plurality of sidewalls defining a peripheral shape; and
a plurality of floating gates in the recesses, each floating gate comprising a conductive material in a recess having the peripheral shape and a generally concave surface within the recess non-planar with the surface of the electrical isolation material.
12. The system of claim 11 wherein the sidewalls are sloped.
13. The system of claim 11 wherein there are four sidewalls and the peripheral shape comprises a rectangle.
14. The system of claim 11 wherein the electrical isolation material comprises an oxide and the conductive material comprises polysilicon or a metal.