Capacitor layout orientation
View Patent ↗The disclosed embodiments relate to a plurality of capacitive memory elements disposed on a substrate. The substrate may comprise a processor, a memory device or other integrated circuit device. The capacitive memory elements may have a generally oblong shape and may be capacitive elements. The capacitive memory elements may be disposed in a slanted orientation. The capacitive memory elements may be disposed in a non-orthogonal orientation. The capacitive memory elements may be disposed so that an axis through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate. The axis may not be generally perpendicular with an orthogonal edge of the substrate. The plurality of capacitive memory elements may be arranged in a first row and a second row so that an axis through one of the plurality of capacitive memory elements located in the first row does not form an axis of any capacitive memory element in the second row.
1. A plurality of generally elliptical capacitive memory elements, each capacitive memory element having a first electrode with an interior portion, the first electrode having a pair of concentric sidewalls that are generally concentric in a plane that is parallel to a surface of a substrate on which the capacitive memory elements are disposed, wherein the plurality of capacitive memory elements are disposed on the substrate so that an axis that runs longitudinally through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate.
2. The plurality of capacitive memory elements set forth in claim 1 wherein the axis is not generally perpendicular with an orthogonal edge of the substrate.
3. The plurality of capacitive memory elements set forth in claim 1 wherein the substrate comprises a processor.
4. The plurality of capacitive memory elements set forth in claim 1 wherein the substrate comprises a memory device.
5. The plurality of capacitive memory elements set forth in claim 1 wherein the substrate comprises an integrated circuit device.
6. The plurality of capacitive memory elements set forth in claim 1 wherein each of the plurality of capacitive memory elements is slanted with respect to the edge of the substrate.
7. An integrated circuit device, comprising:
a substrate;
a memoty array that includes a plurality of memory cells disposed on a face of the substrate, the memory array comprising a plurality of capacitive memory elements, each of the capacitive memory elements being associated with one of the plurality of memory cells, each capacitive memory element having a first electrode a that is circumscribed by a sidewall, wherein generally all of the sidewall is substantially perpendicular to the face of the substrate, and wherein the plurality of capacitive memory elements are disposed on the substrate so that an axis that runs longitudinally through one of the plurality of capacitive memory elements is not generally parallel with an edge of the substrate.
8. The integrated circuit device set forth in claim 7 wherein the axis is not generally perpendicular with an orthogonal edge of the substrate.
9. The integrated circuit device set forth in claim 7 wherein the substrate comprises a processor.
10. The integrated circuit device set forth in claim 7 wherein the substrate comprises a memory device.
11. The integrated circuit device set forth in claim 7 wherein each of the plurality of capacitive memory elements is slanted with respect to the edge of the substrate.