Selectable clock input
View Patent ↗A memory device having a mode register with a selectable bit which sets the memory device to operate with a selected one of a plurality of possible clock input signals, for example, a single clock input or differential clock input.
1. A mode register comprising:
at least one programmable storage location for storing information identifying a type of clock input signal which will be used during operation of a memory device at a specified frequency.
2. The mode register according to claim 1 wherein said programmable storage location has a default setting for one type of clock input signal.
3. The mode register according to claim 2 wherein said one type of clock input signal is a single clock input signal.
4. The mode register according to claim 2 wherein said one type of clock input signal is a differential clock input signal.
5. The mode register according to claim 1 wherein said programmable storage location stores information indicating at least one of a first type of clock input signal and a second type of clock input signal.
6. The mode register according to claim 5 wherein said first type of clock input signal is a single clock input signal and said second type of clock input signal is a differential clock input signal.
7. A control circuit for a memory device, comprising:
a mode register having at least one programmable storage location for storing information identifying a type of clock input signal which will be used during operation of a memory device at a specified frequency; and
a logic circuit responsive to contents of said mode register for operating said memory device.
8. The control circuit according to claim 7 wherein said programmable storage location has a default setting for one type of clock input signal.
9. The control circuit according to claim 8 wherein said one type of clock input signal is a single clock input signal.
10. The control circuit according to claim 8 wherein said one type of clock input signal is a differential clock input signal.
11. The control circuit according to claim 7 wherein said programmable storage location stores information indicating at least one of a first type of clock input signal and a second type of clock input signal.
12. The control circuit according to claim 11 wherein said first type of clock input signal is a single clock input signal and said second type of clock input signal is a differential clock input signal.
13. The control circuit according to claim 7 , wherein said memory device is capable of operating in response to more than one clock input signal.