IP Library › Granted Patent US 6,900,685

Granted Patent B2

US 6,900,685 · App. 10/147,645 · Granted May 31, 2005

Tunable delay circuit

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Quick Facts

Patent No.: US 6,900,685
App. No.: 10/147,645
Granted: May 31, 2005
Kind: B2

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Abstract

A delay circuit delays an input signal to produce an output signal. The input and output signals have a delay which is based on a signal relationship between the input signal and a reference signal. The delay circuit includes configurable devices to vary the reference signal to adjust the delay between the input and output signals.

Claims (69)

1. A circuit comprising:

a comparator including:

a first stage for receiving an input signal; and

a second stage connected to the first stage for receiving a reference signal to output an output signal delayed by an amount of time based on a signal relationship between the input and reference signals; and

a reference generator connected to the comparator, the reference generator including a plurality of configurable transistors to vary the reference signal to adjust a delay between the input and output signals, wherein at least one of the configurable transistors includes a configurable gate-to-drain connection.

2. A circuit comprising:

a comparator including:

a first stage for receiving an input signal; and

a pullup device connected between a first supply node and a pullup node common to the first and second stages; and

3. The circuit of claim 2 , wherein the comparator further includes:

a pulldown device connected between a second supply node and a pulldown node common to the first and second stages.

4. A circuit comprising:

a comparator including:

a first stage for receiving an input signal; and

a reference generator connected to the comparator, the reference generator including a plurality of configurable devices to vary the reference signal to adjust a delay between the input and output signals, wherein the configurable devices include transistors having configurable drain-to-source connections.

5. The circuit of claim 4 , wherein the transistors having configurable drain-to-source connections include configurable gate-to-source connections.

6. The circuit of claim 5 , wherein the transistors having configurable drain-to-source connections includes configurable gate-to-gate to connections.

7. A circuit comprising:

a comparator including a comparator reference node to receive a reference signal, an input node to receive an input signal, and an output node to output an output signal; and

a reference generator including:

a plurality of selectable level generators, each of the selectable level generators including a plurality of configurable devices configured in a different configuration to output a selectable signal; and

a multiplexer connected between the selectable level generators and the comparator reference node for selecting the selectable signal from selectable level generators to adjust a delay between the input and output signals.

8. The circuit of claim 7 , wherein the comparator further includes:

a first pair of transistors including a first common gate for receiving the input signal; and

a second pair of transistors connected to the first pair of transistors, the second pair of transistors including a second common gate for receiving the selectable signal and including a common drain for outputting the output signal.

9. The circuit of claim 8 , wherein the selectable level generators further include a plurality of configurable devices connected to the comparator reference node.

10. The circuit of claim 9 , wherein each of the selectable level generators further includes:

a load transistor connected between the selectable output node and a first supply node; and

an output transistor connected between the selectable output node and a second supply node.

11. A method of processing a signal, the method comprising:

receiving an input signal;

receiving a reference signal;

producing an output signal having a delay in comparison to the input signal; and

varying the reference signal to adjust the delay, wherein varying includes configuring a plurality of transistors to adjust the delay, and wherein at least one of the transistors includes a configurable drain-to-source connection.

12. The method of claim 11 , wherein producing an output signal includes comparing the input signal and the reference signal.

13. A method of processing a signal, the method comprising:

receiving an input signal;

receiving a reference signal;

producing an output signal having a delay in comparison to the input signal, wherein producing includes comparing the input signal and the reference signal; and

varying the reference signal to adjust the delay, wherein varying includes configuring a plurality of transistors to adjust the delay, and wherein configuring a plurality of transistors includes configuring a drain-to-source connection of at least one of the plurality of transistors.

14. A circuit comprising:

a first pair of transistors having a common gate for receiving an input signal; a first source, a second source, and a common drain;

a second pair of transistors having a first source, a second source, a common gate for receiving a reference signal, and a common drain for outputting an output signal;

a pullup device connected to the common drain of the first pair of transistors, to the first sources of the first and second pairs of transistors, and to a first supply node;

a pulldown device connected to the common drain of the first pair of transistors, to the second sources of the first and seconds pair of transistors, and to a second supply node; and

a reference generator including a plurality of configurable devices connected to the common gate of the second pair of transistors for providing a reference signal.

15. The circuit of claim 14 , wherein the pullup device includes a transistor having a gate connected to the common drain of the first pair of transistors, a drain connected to the first source of the second pair of transistors, and a source connected to the first supply node.

16. The circuit of claim 14 , wherein the pulldown device includes a transistor having a gate connected to the common drain of the first pair of transistors, a source connected to the second sources of the first and second pairs of transistors, and a source connected to the second supply node.

17. The circuit of claim 14 , wherein the plurality of configurable devices includes a number of transistors connected between the first and second supply nodes.

18. The circuit of claim 17 , wherein at least one of the number of transistors includes a configurable drain-to-source connection.

19. The circuit of claim 17 , wherein at least one of the number of transistors includes a configurable gate-to-source connection.

20. The circuit of claim 17 , wherein at least one of the number of transistors includes a configurable gate-to-gate connection.

21. A circuit comprising:

a first pair of transistors having a common gate for receiving an input signal; a first source, a second source, and a common drain;

a second pair of transistors having a first source, a second source, a common gate for receiving a reference signal, and a common drain for outputting an output signal;

a pullup device connected to the common drain of the first pair of transistors, to the first sources of the first and second pairs of transistors, and to a first supply node;

a pulldown device connected to the common drain of the first pair of transistors, to the second sources of the first and seconds pair of transistors, and to a second supply node; and

a reference generator including a bias stage with a bias node for providing a bias signal, and an output stage connect to the bias node and the common gate of the second pair of transistors for providing a reference signal based on the bias signal.

22. The circuit of claim 21 , wherein the pullup device includes a transistor having a gate connected to the common drain of the first pair of transistors, a drain connected to the first source of the second pair of transistors, and a source connected to the first supply node.

23. The circuit of claim 22 , wherein the pulldown device includes a transistor having a gate connected to the common drain of the first pair of transistors, a source connected to the second sources of the first and second pairs of transistors, and a source connected to the second supply node.

24. The circuit of claim 21 , wherein the bias stage includes:

a first transistor connected between the first supply node and the bias node; and

a second transistor connected between the bias node and the second supply node.

25. The circuit of claim 24 , wherein the output stage includes:

a first transistor connected between the first supply node and the common gate of the second pair of transistors; and

a second transistor connected between the common gate of the second pair of transistors and the second supply node.

Assignments (1)

ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2010

From: MICRON TECHNOLOGY, INC.

To: ROUND ROCK RESEARCH, LLC

Reel/Frame 023786/0416 →