IP Library › Granted Patent US 5,259,924
Granted Patent Utility
US 5,259,924 · App. 07/865,087

Integrated circuit fabrication process to reduce critical dimension loss during etching

Inventors: Viju K. Mathews, Ardavan Niroomand, Guy T. Blalock, Pierre C. Fazan
Patented Case View Patent ↗
Granted: Nov 9, 1993 Filed: Apr 8, 1992
Inventors
Viju K. Mathews
Ardavan Niroomand
Guy T. Blalock
Pierre C. Fazan
Assignee (at issue)
Micron Technology, Inc.

This patent predates the USPTO's electronic file wrapper — prosecution documents from this era exist only in the Patent Office's paper records. A certified copy of the file history can be ordered from the USPTO's paper archives.

Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 5,259,924
App. No.
07/865,087
Filed
1992-04-08
Granted
1993-11-09
Kind
A