Integrated circuit package having reduced interconnects
View Patent ↗A technique for making an integrated circuit package. Specifically, a stacked memory device is provided with minimal interconnects. Memory die are stacked on top of each other and electrically coupled to a substrate. Thru vias are provided in the substrate and/or memory die to facilitate the electrical connects without necessitating a complex interconnect technology between each of the interfaces. Wire bonds are used to complete the circuit package.
1. An integrated circuit package comprising:
a substrate having first conductive pads thereon;
a first die having a circuit side and a backside, wherein the backside is coupled to the substrate by a layer of at least one of a paste, epoxy, or film, and wherein the circuit side has second conductive pads thereon; and
a second die stacked on the first die, the second die having a circuit side and a backside and extending through said second die having connections, the connections on the backside of the second die being coupled to respective second conductive pads on the circuit side of the first die and the connections on the circuit side of the second die being coupled to the first conductive pads on the substrate, such that the circuit side of the first die is electrically coupled to the substrate through the connections.
2. The integrated circuit package, as set forth in claim 1 , wherein the first die comprises a memory die.
3. The integrated circuit package, as set forth in claim 1 , wherein the second die comprises a memory die.
4. The integrated circuit package, as set forth in claim 1 , wherein the connections on the backside of the second die are coupled to the second conductive pads on the circuit side of the first die via solder balls.
5. The integrated circuit package, as set forth in claim 1 , wherein each of the connections through the second die comprises:
a ball pad on the backside of the second die;
a bond pad on the circuit side of the second die; and
a conductive path electrically coupled between the ball pad and the bond pad.
6. The integrated circuit package, as set forth in claim 1 , wherein the connections on the circuit side of the second die are coupled to the first conductive pads on the substrate via bondwires.
7. A system comprising:
a processor; and
an integrated circuit package coupled to the processor and comprising:
a substrate having first conductive pads thereon;
a first die having a circuit side and a backside, wherein the backside is coupled to the substrate by a layer of at least one of a paste, epoxy, or film, and wherein the circuit side has second conductive pads thereon; and
a second die stacked on the first die, the second die having a circuit side and a backside and extending through said second die having connections, the connections on the backside of the second die being coupled to respective second conductive pads on the circuit side of the first die and the connections on the circuit side of the second die being coupled to the first conductive pads on the substrate, such that the circuit side of the first die is electrically coupled to the substrate through the connections.
8. The system, as set forth in claim 7 , wherein the first die comprises a memory die.
9. The system, as set forth in claim 7 , wherein the second die comprises a memory die.
10. The system, as set forth in claim 7 , wherein the connections on the backside of the second die are coupled to the second conductive pads on the circuit side of the first die via solder balls.
11. The system, as set forth in claim 7 , wherein each of the connections through the second die comprises:
a ball pad on the backside of the second die;
a bond pad on the circuit side of the second die; and
a conductive path electrically coupled between the ball pad and the bond pad.
12. The system, as set forth in claim 7 , wherein the connections on the circuit side of the second die are coupled to the first conductive pads on the substrate via bondwires.