Pixel for CMOS image sensor having a select shape for low pixel crosstalk
View Patent ↗A novel CMOS image unit pixel layout having a photodiode including an optically optimized square image sensing region. The square image sensing layout provides for reduced electrical and color crosstalk and improved modulation transfer function (MTF) between neighboring pixels of an array of pixels.
1. An array comprising:
a plurality of CMOS pixels, each CMOS pixel comprising:
a substantially square image sensing region, wherein a distance between the image sensing regions of neighboring pixels is optimized to reduce crosstalk between the neighboring pixels and the distance is at least 3.8 micrometers along a first axis and at least 4 micrometers along a second axis; and
a substantially hemispherical microlens positioned over the image sensing region of each pixel.
2. The array of pixels of claim 1 , wherein the distance is further optimized to improve MTF.
3. The array of claim 1 , wherein the first axis and the second axis are perpendicular.
4. The array of claim 1 , wherein sides of each CMOS pixel are about 8 micrometers.
5. An improved CMOS imaging array having a plurality of pixels for use in a CMOS imaging system, the improvement of each pixel comprising:
a substantially square image sensing region configured to increase the distance between the image sensing regions of neighboring pixels, wherein the distance is at least 3.8 micrometers along a first axis and at least 4 micrometers along a second axis; and
a substantially hemispherical microlens positioned over the image sensing region.
6. The CMOS imaging array of claim 5 , wherein the position of the substantially hemispherical microlens is configured to increase an effective fill factor.
7. The CMOS imaging array of claim 6 , wherein the improvement of each pixel further comprises:
a. a transfer transistor having a drain coupled to the cathode of the photodiode, a gate controlled by a control signal, Tx, and a source coupled to a floating sensing node;
b. a reset transistor having a drain coupled to a reset potential, a gate controlled by a control signal, Rx, and a source coupled to the floating sensing node; and
c. a source follower coupled between the floating sensing node and an output of the unit pixel, the source follower controlled by a select signal.
8. The CMOS imaging array of claim 7 , wherein the transfer transistor, the reset transistor, and the source follower are positioned along at least two sides of the pixel.
9. The CMOS imaging array of claim 7 , wherein the reset transistor is a depletion mode transistor.