IP Library › Granted Patent US 6,373,764
Granted Patent Utility
US 6,373,764 · Confirmation No. 6742

SEMICONDUCTOR MEMORY DEVICE ALLOWING STATIC-CHARGE TOLERANCE TEST BETWEEN BIT LINES

Inventor: Shinya Fujioka
Patented Case View Patent ↗ View Publication ↗
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 Code Description Pages PDF
2001-02-23 TRNA Transmittal of New Application 1 View
2001-02-23 SPEC Specification 17 View
2001-02-23 CLM Claims 4 View
2001-02-23 ABST Abstract 1 View
2001-02-23 DRW Drawings-only black and white line drawings 8 View
2001-02-23 OATH Oath or Declaration filed 3 View
2001-02-23 TRNA Transmittal of New Application 1 View
2001-02-23 SPEC Specification 17 View
2001-02-23 CLM Claims 4 View
2001-02-23 ABST Abstract 1 View
2001-02-23 DRW Drawings-only black and white line drawings 8 View
2001-02-23 OATH Oath or Declaration filed 3 View
2001-02-23 TRNA Transmittal of New Application 1 View
2001-02-23 SPEC Specification 17 View
2001-02-23 CLM Claims 4 View
2001-02-23 ABST Abstract 1 View
2001-02-23 DRW Drawings-only black and white line drawings 8 View
2001-02-23 OATH Oath or Declaration filed 3 View
2001-02-23 TRNA Transmittal of New Application 1 View
2001-02-23 SPEC Specification 17 View
2001-02-23 CLM Claims 4 View
2001-02-23 ABST Abstract 1 View
2001-02-23 DRW Drawings-only black and white line drawings 8 View
2001-02-23 OATH Oath or Declaration filed 3 View
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Quick Facts
Patent No.
US 6,373,764
App. No.
09/790,573
Filed
2001-02-23
Granted
2002-04-16
Pub. No.
US20010017807A1
Examiner
PHUNG, ANH K
Art Unit
2824
PTA
0 days