IP Library Granted Patent US 7,376,207
Granted Patent B2
US 7,376,207 · App. 09/794,285 · Granted May 20, 2008

Apparatus for receiving and recovering frequency shift keyed symbols

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Quick Facts
Patent No.
US 7,376,207
App. No.
09/794,285
Granted
May 20, 2008
Kind
B2
Abstract

A receiver architecture for receiving an FSK signal having a predetermined number of modulation levels includes a selectivity filter ( 206 ) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter bandwidth of about one-half the bandwidth of a pre-modulation filter in a transmitter sending the FSK signal. A discriminator ( 208 ) is coupled to the selectivity filter for demodulating the signal. A symbol recovery processor ( 210 ) is coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

Claims (48)

1. A receiver architecture for receiving a signal and recovering symbols transmitted over a frequency shift keyed (FSK) channel using a predetermined number of modulation levels, the symbols transmitted using a pre-modulation filter having a bandwidth, the receiver architecture comprising:

a selectivity filter for selectively passing a wanted channel and rejecting unwanted channels, the selectivity filter having a filter bandwidth of about one-half the bandwidth of the pre-modulation filter;

a discriminator coupled to the selectivity filter for demodulating the signal; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

2. The receiver architecture of claim 1 , wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed such that a post-detection filter is not required in the receiver architecture.

3. The receiver architecture of claim 1 , wherein the symbol recovery processor is programmed such that the templates are optimized with a bandwidth equal to the bandwidth of the pre-modulation filter divided by approximately the square root of three.

4. The receiver architecture of claim 1 , wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level Gaussian frequency shift keyed (2-GFSK) channel having a data rate of 1 Mbps.

5. The receiver architecture of claim 1 , wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level frequency shift keyed (2-FSK) channel at data rates of 0.8 and 5.0 Mbps, and in a four-level frequency shift keyed (4-FSK) channel at data rates of 1.6 and 10.0 Mbps.

6. An integrated circuit for use in a receiver for receiving a signal and recovering symbols transmitted over a frequency shift keyed (FSK) channel using a predetermined number of modulation levels, the symbols transmitted using a pre-modulation filter having a bandwidth, the integrated circuit comprising:

a selectivity filter for selectively passing a wanted channel and rejecting unwanted channels, the selectivity filter having a filter bandwidth of about one-half the bandwidth of the pre-modulation filter;

a discriminator coupled to the selectivity filter for demodulating the signal; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

7. The integrated circuit of claim 6 , wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed such that a post-detection filter is not required in the integrated circuit.

8. The integrated circuit of claim 6 , wherein the symbol recovery processor is programmed such that templates are optimized with a bandwidth equal to the bandwidth of the pre-modulation filter divided by approximately the square root of three.

9. The integrated circuit of claim 6 , wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level Gaussian frequency shift keyed (2-GFSK) channel having a data rate of 1 Mbps.

10. The integrated circuit of claim 6 , wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level frequency shift keyed (2-FSK) channel at data rates of 0.8 and 5.0 Mbps, and in a four-level frequency shift keyed (4-FSK) channel at data rates of 1.6 and 10.0 Mbps.

11. An apparatus for receiving a signal and recovering symbols transmitted over a frequency shift keyed (FSK) channel using a predetermined number of modulation levels, the symbols transmitted using a pre-modulation filter having a bandwidth, the apparatus comprising:

a selectivity filter for selectively passing a wanted channel and rejecting unwanted channels, the selectivity filter having a filter bandwidth of about one-half the bandwidth of the pre-modulation filter;

a discriminator coupled to the selectivity filter for demodulating the signal; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

12. A receiver for receiving a signal and recovering symbols transmitted over a frequency shift keyed (FSK) channel using a predetermined number of modulation levels, the symbols transmitted using a pre-modulation filter having a bandwidth, the receiver comprising:

a down-converter for down-converting the signal;

a selectivity filter coupled to the down-converter for selectively passing a wanted channel and rejecting unwanted channels, the selectivity filter having a filter bandwidth of about one-half the bandwidth of the pre-modulation filter;

a discriminator coupled to the selectivity filter for demodulating the signal; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

13. A transceiver for receiving a signal and recovering symbols transmitted over a frequency shift keyed (FSK) channel using a predetermined number of modulation levels, the symbols transmitted using a pre-modulation filter having a bandwidth, the transceiver comprising:

a transmitter for transmitting a communication signal;

a communications processor coupled to the transmitter for controlling the transmitter; and

a receiver coupled to the communications processor for receiving the signal, the receiver comprising:

a down-converter for down-converting the signal;

a selectivity filter for selectively passing a wanted channel and rejecting unwanted channels, the selectivity filter having a filter bandwidth of about one-half the bandwidth of the pre-modulation filter;

a discriminator coupled to the selectivity filter for demodulating the signal; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

14. The transceiver of claim 13 , wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed such that a post-detection filter is not required in the receiver.

15. The transceiver of claim 13 , wherein the symbol recovery processor is programmed such that the templates are optimized with a bandwidth equal to the bandwidth of the pre-modulation filter divided by approximately the square root of three.

16. The transceiver of claim 13 , wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level Gaussian frequency shift keyed (2-GFSK) channel having a data rate of 1 Mbps.

17. The transceiver of claim 13 , wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level frequency shift keyed (2-FSK) channel at data rates of 0.8 and 5.0 Mbps, and in a four-level frequency shift keyed (4-FSK) channel at data rates of 1.6 and 10.0 Mbps.

18. A wireless headset for a two-way portable communication device, the wireless headset for receiving a wireless signal and recovering symbols transmitted over a frequency shift keyed (FSK) channel using a predetermined number of modulation levels, the symbols transmitted using a pre-modulation filter having a bandwidth, the wireless headset comprising:

a first transducer for receiving a speech input from a user;

a transmitter coupled to the first transducer for transmitting to the two-way portable communication device a communication signal comprising the speech input;

a communications processor coupled to the transmitter for controlling the transmitter;

a receiver coupled to the communications processor for receiving the wireless signal from the two-way portable communication device; and

a second transducer coupled to the receiver for conveying to the user a message received in the digital wireless signal, and

wherein the receiver comprises:

a down-converter for down-converting the wireless signal;

a selectivity filter for selectively passing a wanted channel and rejecting unwanted channels, the selectivity filter having a filter bandwidth of about one-half the bandwidth of the pre-modulation filter;

a discriminator coupled to the selectivity filter for demodulating the wireless signal; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a maximum likelihood sequence estimation (MLSE) technique utilizing N states for each symbol time, wherein N equals the predetermined number of modulation levels, and wherein templates used in the MLSE for symbol transitions are optimized with a bandwidth substantially less than the bandwidth of the pre-modulation filter.

Assignments (15)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2016
From: FREESCALE SEMICONDUCTOR, INC.
To: NORTH STAR INNOVATIONS INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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To: MORGAN STANLEY SENIOR FUNDING, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037356/0143 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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