Processor architecture and a method of processing
View Patent ↗A process and architecture to simplify the implementation of a high-speed scheduler. A traditional packet based scheduler works the length of the packet. Instead, the present invention uses a transmit queue that determines how many times a portion of a packet needs to be transmitted independent of the process to modify or transform the packet. The packet could be an ATM cell, it could be a fabric cell, or it could be a portion of a frame-based transmission of the packet. As a result, the transmit queue need only determine how many times (times to transmit (TTT)) to schedule transmission of part of the packet. The determined TTT from the transit queue takes into account the packet-based modifications that will be performed on the packet. The TTT is used to determine how many cells the packet needs to be divided into. In another illustrative embodiment, the number of cells or the TTT is determined prior to adding or removing data from the packet. In a further illustrative embodiment, the transmit queue is separate from the circuitry that modifies the packet. In other words, determining the TTT for a packet is separate from the process of modifying the packet for transmission.
1. A method of processing comprising:
(a) receiving a data packet;
(b) modifying the data packet employing information associated with a destination of the data packet to determine what modifications of the data packet are needed for transmission to the destination; and
(c) before step (b), determining based on the information a number of times to transmit (TTT) portions of the data packet to transmit the entire packet to the destination.
2. The method of claim 1 further comprising:
(d) providing first circuitry for determining the number of TTT portions; and
(e) providing second circuitry different from the first circuitry for modifying the data packet.
3. The method of claim 1 wherein the determining is independent of the modifying.
4. The method of claim 1 wherein the TTT portions are sized according to a transmission standard.
5. The method of claim 1 wherein the number of TTT portions is based on an actual length of the data packet.
6. The method of claim 1 further comprising determining the entire packet has been transmitted based on counting transmitted TTT portions.
7. The method of claim 1 wherein the entire packet is an entire modified packet.
8. The method of claim 1 wherein the data packet is received over a communications network.
9. The method of claim 1 wherein the modifying includes modifying the data packet for transmission over a communications network.
10. The method of claim 1 wherein the modifying includes adding or removing data from the data packet.
11. The method of claim 1 wherein the data packet is an ATM cell.
12. The method of claim 1 wherein the data packet is a fabric cell.
13. The method of claim 1 wherein the data packet is a portion of a frame-based transmission of a data.
14. A routing switch processor, comprising:
an interface that receives a data packet over a communications network;
a processing engine, coupled to the interface, that modifies the data packet for transmission; and
a transmit queue, coupled to the interface and the processing engine, that determines, based on information associated with the destination of the data packet received by the interface, a number of times to transmit (TTT) portions of the data packet to transmit the entire data packet before the processing engine modifies the data packet, wherein the processing engine employs the information to determine what modifications of the data packet are needed for transmission to the destination.
15. The routing switch processor as recited in claim 14 wherein the routing switch processor operates at wire-speed.
16. The routing switch processor as recited in claim 14 wherein the transmit queue schedules the processing engine to transmit data based on the number of TTT.
17. The routing switch processor as recited in claim 14 wherein the transmit queue employs a counter to determine if transmission by the routing switch processor is complete based on the number of TTT.
18. The routing switch processor as recited in claim 14 wherein the transmit queue determines the number of TTT based on the length of the data packet received by the interface and a size of packets to be transmitted by the routing switch processor.