Patent Assignment
Reel/Frame 035090/0477
Assignment of Assignor's Interest
Recorded: 2015-02-24
Pages: 36
Assignor
LSI CORPORATION
Executed: 2014-11-14
Assignee
INTEL CORPORATION
2200 MISSION COLLEGE BOULEVARD, SANTA CLARA, CALIFORNIA, 95054
Covered Properties
(443)
Scheduling Methods and Apparatus Based on Adjusted Channel Capacity
PCT:
PCT/US2007/062201 ↗
Methods and Apparatus for Controlling Latency Variation in a Packet Transfer Network
PCT:
PCT/US2007/062210 ↗
Network-Based Data Traffic Detection and Control
PCT:
PCT/US2007/062639 ↗
Interface with Multilevel Packet Preemption Based on Balancing of Start and End Indicators
PCT:
PCT/US2007/067281 ↗
Direct Digital Synthesis of Signals Using Maximum Likelihood Bit-Stream Encoding
PCT:
PCT/US2012/062175 ↗
Software Digital Front End (Softdfe) Signal Processing
PCT:
PCT/US2012/062179 ↗
Vector Processor Having Instruction Set with Vector Convolution Funciton for Fir Filtering
PCT:
PCT/US2012/062182 ↗
Processor Having Instruction Set with User-Defined Non-Linear Functions for Digital Pre-Distortion (Dpd) and Other Non-Linear Applications
PCT:
PCT/US2012/062186 ↗
Digital Processor Having Instruction Set with Complex Exponential Non-Linear Function
PCT:
PCT/US2012/062191 ↗
Block-Based Crest Factor Reduction (Cfr)
PCT:
PCT/US2012/062195 ↗
Telecommunication System with Detection and Control of Packet Collisions
Patent:
5,513,174 →
Application:
08/350,926 →
Single Chip Universal Protocol Multi-Function Atm Network Interface
Patent:
5,802,287 →
Application:
08/510,643 →
Transmission System for Transmitting and Detecting the Beginning of the Frame of a Frame Synchronized Signal
Patent:
5,671,227 →
Application:
08/513,316 →
Method and Apparatus for Reducing Data Delay Within a Multi-Channel Shared-Circuit Data Processing Environment
Patent:
5,790,072 →
Application:
08/537,568 →
Real-Time Hardware Method and Apparatus for Reducing Queue Processing
Patent:
6,201,807 →
Application:
08/607,730 →
Method and Apparatus for Fast Synchronization of T1 Extended Superframes
Patent:
5,621,773 →
Application:
08/611,327 →
Atm Communication System Interconnect/Termination Unit
Patent:
5,726,985 →
Application:
08/612,373 →
Shared Memory Fabric Architecture for Very High Speed Atm Switches
Patent:
5,831,980 →
Application:
08/710,207 →
Scheduler Design for Atm Switches, and Its Implementation in a Distributed Shared Memory Architecture
Patent:
5,959,993 →
Application:
08/714,005 →
Method and Apparatus for Controlling Data Transfer Rates Using Marking Threshold in Asynchronous Transfer Mode Networks
Patent:
5,905,711 →
Application:
08/751,045 →
Sonet Physical Layer Device Having Atm and Ppp Interfaces
Patent:
6,075,788 →
Application:
08/867,249 →
Method and Apparatus for Reducing Noise in Speech and Audio Signals
Patent:
6,035,048 →
Application:
08/877,909 →
Multiple Line Framer Engine
Patent:
6,331,988 →
Application:
08/903,588 →
Multiple Tone Detection Using Out-of-Band Background Detector
Patent:
6,128,370 →
Application:
08/906,818 →
In-Band Device Configuration Protocol for Atm Transmission Convergence Devices
Patent:
6,272,144 →
Application:
08/939,746 →
Simplified Data Link Protocol Processor
Patent:
6,263,443 →
Application:
08/947,538 →
Method and Apparatus for Synchronizing Digital Speech Communications
Patent:
5,953,695 →
Application:
08/959,888 →
Atm Communication System Interconnect/Termination Unit
Patent:
6,373,846 →
Application:
09/036,966 →
Echo Canceler Including Subband Echo Suppressor
Patent:
6,442,275 →
Application:
09/154,991 →
Method and Apparatus for Processing Data Packets
Patent:
6,304,553 →
Application:
09/156,432 →
Method and Apparatus for Guaranteeing Data Transfer Rates and Delays in Data Packet Networks Using Logarithmic Calendar Queues
Patent:
6,396,843 →
Application:
09/182,884 →
Mixed-Mode Next/Echo Canceller for Pulse Amplitude Modulated (Pam) Signals
Patent:
6,584,159 →
Application:
09/188,625 →
Second Order Lms Tap Update Algorithm with High Tracking Capability
Patent:
6,202,075 →
Application:
09/206,519 →
Low-Complexity Dmt Transceiver
Patent:
6,771,695 →
Application:
09/364,411 →
Method and Apparatus for Interfacing Multiple Communication Devices to a Time Division Multiplexing Bus
Patent:
7,042,895 →
Application:
09/405,205 →
Method and Apparatus for Interfacing Multiple Data Channels to a Bus
Patent:
6,895,016 →
Application:
09/427,961 →
Single-Bit Timestamps for Data Transfer Rate and Delay Guarantees in a Packet Network
Patent:
6,654,345 →
Application:
09/432,976 →
Communications System with Symmetrical Interfaces and Associated Methods
Patent:
6,775,302 →
Application:
09/459,439 →
Communications System and Associated Methods with Out-of-Band Control
Patent:
6,909,727 →
Application:
09/459,831 →
Communications System and Associated Deskewing Methods
Patent:
6,678,842 →
Application:
09/459,848 →
Communications System Including Lower Rate Parallel Electronics with Skew Compensation and Associated Methods
Patent:
6,675,327 →
Application:
09/460,165 →
Sonet Physical Layer Device Having Atm and Ppp Interfaces
Patent:
6,839,352 →
Application:
09/464,267 →
Digital Adaptive Equalizer for T1/E1 Long Haul Transceiver
Patent:
6,980,592 →
Application:
09/471,806 →
Method for Designing All Pass Digital Filters
Patent:
6,526,429 →
Application:
09/549,753 →
Method for Reconstructing an Aggregate Atm Cell Stream and Related Device
Patent:
6,717,960 →
Application:
09/585,476 →
Method and Apparatus for Guaranteeing Data Transfer Rates and Delays in Asynchronous
Patent:
6,904,045 →
Application:
09/587,149 →
Method and Apparatus for Providing Differentiated Quality of Service Guarantees in Scalable Packet Switches
Patent:
7,027,457 →
Application:
09/599,250 →
System and Method for Reducing Jitter in a Packet Transport System
Patent:
7,145,908 →
Application:
09/648,996 →
Multistage Digital Cross Connect with Integral Frame Timing
Multistage Digital Cross Connect with Synchronized Configuration Switching
Time Slot Interchanger
Link Layer Device and Method of Translating Packets Between Transport Protocols
Processor Architure and a Method of Processing
Patent:
7,116,680 →
Application:
09/798,112 →
Processor Architecture and a Method of Processing
Patent:
6,687,803 →
Application:
09/798,130 →
Function Interface System and Method of Processing Issued Functions Between Co-Processors
Virtual Reassembly System and Method of Operation Thereof
Checksum Engine and a Method of Operation Thereof
Multi-Protocol Bus System and Method of Operation Thereof
Patent:
6,925,514 →
Application:
09/821,892 →
External Device Transmission System and a Fast Pattern Processor Employing the Same
Event Edge Synchronization System and Method of Operation Thereof
Patent:
7,250,797 →
Application:
09/821,898 →
Virtual Segmentation System and Method of Operation Thereof
Patent:
7,009,979 →
Application:
09/822,655 →
Method and Apparatus for Guaranteeing Data Transfer Rates and Enforcing Conformance with Traffic Profiles in a Packet Network
Detection and Correction Circuit for Blind Equalization Convergence Errors
Efficient High Density Voice Processor
Patent:
7,346,048 →
Application:
09/919,221 →
System and Method for Updating Filter Coefficients and Echo Canceller Including Same
Cipher Block Chaining Mode in Encryption/Decryption Processing
Voice Packet Processor and Method of Operation Thereof
Processor with Reduced Memory Requirements for High-Speed Routing and Switching of Packets
Memory System for Increased Bandwidth
Method for Implementing Dual Link List Structure to Enable Fast Link-List Pointer Updates
Method for encoding/decoding a binary signal state in a fault tolerant environment
Application:
10/026,353 →
Publication:
US 2003/0120966
Methods and Apparatus for Using Multiple Reassembly Memories for Performing Multiple Functions
Methods and Apparatus for Forming Linked List Queue Using Chunk-Based Structure
Processor with Multiple-Pass Non-Sequential Packet Classification Feature
Processor with Packet Data Flushing Feature
Method and Apparatus for Classification of Packet Data Prior to Storage in Processor Buffer Memory
Processor with Packet Processing Order Maintenance Based on Packet Flow Identifiers
Method of Improving the Lookup Performance of Tree-Type Knowledge Base Searches
Method and apparatus for maintaining multicast lists in a data network
Method and Apparatus for Reassembly of Data Blocks Within a Network Processor
Method and Apparatus for Buffer Partitioning Without Loss of Data
Method and Apparatus for Providing Multiple Data Class Differentiation with Priorities Using a Single Scheduling Structure
Method and Apparatus for Switching Between Active and Standby Switch Fabrics with No Loss of Data
Adaptive Threshold Based Jitter Buffer Management for Packetized Data
Method and Apparatus for Establishing a Bound on the Effect of Task Interference in a Cache Memory
Context Switching System for a Multi-Thread Execution Pipeline Loop and Method of Operation Thereof
Processor with Dynamic Table-Based Scheduling Using Linked Transmission Elements for Handling Transmission Request Collisions
Processor with Table-Based Scheduling Using Software-Controlled Interval Computation
Processor with Dynamic Table-Based Scheduling Using Multi-Entry Table Locations for Handling Transmission Request Collisions
Processor with Software-Controlled Programmable Service Levels
Non-Blocking Grooming Switch
Low Power Vector Summation Method and Apparatus
Buffer Management for Merging Packets of Virtual Circuits
Striping Algorithm for Switching Fabric
Patent:
7,586,909 →
Application:
10/269,928 →
Deficit-Based Striping Algorithm
Patent:
7,319,695 →
Application:
10/270,264 →
Method and Apparatus for Improved Play-Out Packet Control Algorithm
Processor for Packet Switching Between Cell Streams with Optional Virtual Channel and Channel Identification Modification
Method and System for Guaranteeing Quality of Service in a Multi-Plane Cell Switch
Method and Apparatus for Ensuring Cell Ordering in Large Capacity Switching Systems and for Synchronizing the Arrival Time of Cells to a Switch Fabric
Weighted Fair Share Scheduler for Large Input-Buffered High-Speed Cross-Point Packet/Cell Switches
Digital Cross-Connect
Backpressure Mechanism for Switching Fabric
Patent:
7,426,185 →
Application:
10/358,678 →
Scheduling Connections in a Multi-Stage Switch to Retain Non-Blocking Properties of Constituent Switching Elements
Duobinary Pulse Shaping for Optical Transmission Systems Employing Pulse Amplitude Modulation Techniques
Devices for Performing Multiple Independent Hardware Acceleration Operations and Methods for Performing Same
Simplified Data Link Protocol Processor
Patent:
40,923 →
Application:
10/417,013 →
Pointer Generation Method and Apparatus for Delay Compensation in Virtual Concatenation Applications
Stall Need Detection and Associated Stall Mechanism for Delay Compensation in Virtual Concatenation Applications
Real Time Tuner for Providing Graphical User Interface
Simulation Framework with Support for Multiple Integrated Circuits Having Potentially Differing Characteristics
Extensible Traffic Generator for Synthesis of Network Data Traffic
Method and Apparatus for Automatic Generation of Multiple Integrated Circuit Simulation Configuration
Traffic Generator with Enhanced Burst Modeling Feature
Processor Configured for Efficient Processing of Single-Cell Protocol Data Units
Parallelized Dynamic Huffman Decoder
Method and System for Wireless Communication with an Integrated Circuit Under Evaluation
Processor with Input Data Block Discard Mechanism for Use in an Oversubscription Condition
Processor with Multiple Linked List Storage Feature
Processor with Continuity Check Cache
Traffic Management Using in-Band Flow Control and Multiple-Rate Traffic Shaping
Processor with Script-Based Performance Monitoring
Internal Memory Controller Providing Configurable Access of Processor Clients to Memory Instances
Processor with Scheduler Architecture Supporting Multiple Distinct Scheduling Algorithms
Access Control List Constructed as a Tree of Matching Tables
Directed Graph Approach for Constructing a Tree Representation of an Access Control List
Link Layer Device with Configurable Address Pin Allocation
Method and Apparatus for Guaranteeing Data Transfer Rates and Delays in Data Packet Networks Using Generalized Discrete Data Transfer Rate Approach
Link Layer Device with Non-Linear Polling of Multiple Physical Layer Device Ports
Processor Having Split Transmit and Receive Media Access Controller with Reduced Complexity Interface
System and Method for Tokening Documents
Processor with Instruction-Based Interrupt Handling
System and Method of Xml Query Processing
Digital Service Hierarchy Level 3 (DS3) Application Detection
Communications System with Symmetrical Interfaces and Associated Methods
Network-Based Data Transport Architecture
Frame Mapping Scheduler for Scheduling Data Blocks Using a Mapping Table and a Weight Table
Virtual Reassembly System and Method of Operation Thereof
Frame Mapping Scheduler with Compressed Mapping Table
Method and Apparatus for Improved Data Channel Transmission in a Digital Network
Adaptive Peak Windowing for Crest Factor Reduction in a Communication System Transmitter
Apparatus and Method for Processing Cells in a Atm Adaptation Layer Device in a Communications System That Exhibits Cell Delay Variation
Apparatus and Method for Handling Lost Cells in a Communications System
Multi-Protocol Bus System and Method of Operation Thereof
Connection Memory for Tributary Time-Space Switches
Controlling Timeslot Delay in a Digital Communication System
Method for Encoding/Decoding a Binary Signal State in a Fault Tolerant Environment
Methods and Apparatus for Minimizing Sequence Identifier Difference of Simultaneously Transmitted Cells
Configurable Network Connection Address Forming Hardware
Fast Pattern Processor Including a Function Interface System
Method and Apparatus for N+1 Packet Level Mesh Protection
Circuitry for Determining Network Operations in a Network Device by Addressing Lookup Tables with Contents of Protocol Header Fields
Virtual Segmentation System and Method of Operation Thereof
Methods and Apparatus for Reorganizing Cells Buffered After Transmission
Processor with Programmable Configuration of Logical-to-Physical Address Translation on a Per-Client Basis
Low Power Vector Summation Apparatus
Processor with Flexible Clock Configuaration
Virtual Concatenation of Pdh Signals
Methods and apparatus for performing network operations on packets of data in response to content of particular user-specified protocol header fields
Processor with Configurable Association Between Interface Signal Lines and Clock Domains
Switch-Based Network Processor
Flexible Traffic Management and Shaping Processing for Multimedia Distribution
Methods and Apparatus for Updating Data Structures During in-Service Upgrade of Software in Network Processor
Methods and Apparatus for Performing in-Service Upgrade of Software in Network Processor
Two Dimensional Timeout Table Mechanism with Optimized Delay Characteristics
High-Throughput Scheduler with Guaranteed Fairness for Wireless Networks and Other Applications
Wireless Network Scheduling Methods and Apparatus Based on Both Waiting Time and Occupancy
Systems and Methods for Processing Regular Expressions
Link Layer Device with Clock Processing Hardware Resources Shared Among Multiple Ingress and Egress Links
Network-based data traffic detection and control
Methods and Apparatus for Prevention of Excessive Control Message Traffic in a Digital Networking System
High-Throughput Scheduler with Integer-Based Eligible Number Initialization
Port Addressing Method and Apparatus for Link Layer Interface
Yield-Enhancing Device Failure Analysis
Scheduling Methods and Apparatus Based on Adjusted Channel Capacity
Apparatus and Method for Fractional Processing of Cells in a Communications System
Video Processing Architecture Having Reduced Memory Requirement
Interface with Multilevel Packet Preemption Based on Balancing of Start and End Indicators
Dual Leaky Bucket Flow Control Method and System
Methods and Apparatus for Controlling Latency Variation in a Packet Transfer Network
Characterizing Transmission of Data Segments Within a Switch Fabric Using Multiple Counters for Each Destination Node
Methods and Apparatus for Testing Adaptive Timing Characteristics of Packet-Based Timing Protocol
Event Edge Synchronization System and Method of Operation Thereof
Interface with Multiple Packet Preemption Based on Start Indicators of Different Types
Synchronous Transport Signal Mapper with Payload Extraction and Insertion Functionality
Methods and Apparatus for Performing Reduced Complexity Discrete Fourier Transforms Using Interpolation
Parallelized Dynamic Huffman Decoder
In-Band Communication of Alarm Status Information in a Synchronous Transport Communication System
Adaptive Algorithm for Reducing Channel Zapping Time in Multicast Media
Time-Slot Interchange Circuit
Patent:
7,633,936 →
Application:
12/014,162 →
Method and Apparatus for Establishing a Bound on the Effect of Task Interference in a Cache Memory
Method and System for Generating Packet Delay Variation with a Uniform Distribution
Derivative Packet Delay Variation as a Metric for Packet Timing Recovery Stress Testing
Simulating Packet Delay Variation Using Step-Target Delay Method
Connectionless Configurations for Stress Testing Timing and Synchronization in Data Packet Networks
Method and Apparatus for Simulating Packet Delay Variation of a Multi-Switch Network
Hardware Processing of Regular Expressions
A State Machine Compression Using Multi-Character State Transition Instructions
Systems and Methods for Reducing Network Performance Degradation
Detection of Double Talk in Telecommunications Networks
Echo Path Change Detection in Telecommunications Networks
Backpressure Mechanism for Switching Fabric
Hardware Device Comprising Multiple Accelerators for Performing Multiple Independent Hardware Acceleration Operations
Systems and Methods for Compressing State Machine Instructions Using a Two Access Indexing Scheme
Methods and Appratus for Evaluating a Utilization of a System That Provides Connections Using a Normalized Bandwidth Scheme
Methods and Apparatus for Improved Phase Linearity in a Multi-Phase Based Clock/Timing Recovery System
Skip Based Control Logic for First in First Out Buffer
Cache Memory Architecture Having Reduced Tag Memory Size and Method of Operation Thereof
Efficient Implementation of Arithmetical Secure Hash Techniques
Architecture and Implementation Method of Programmable Arithmetic Controller for Cryptographic Applications
Digital Signal Processor Having Instruction Set With One Or More Non-Linear Complex Functions
Digital Signal Processor Having Instruction Set with One or More Non-Linear Functions Using Reduced Look-Up Table
Digital Signal Processor Having Instruction Set with One or More Non-Linear Functions Using Reduced Look-Up Table with Exponentially Varying Step-Size
Digital Signal Processor With One Or More Non-Linear Functions Using Factorized Polynomial Interpolation
Framer/Mapper/Multiplexor Device with 1+1 and Equipment Protection
Communications System with Symmetrical Interfaces and Associated Methods
Digital Signal Processor Having Instruction Set With An Xk Function Using Reduced Look-Up Table
Digital Signal Processor Having Instruction Set With An Exponential Function Using Reduced Look-Up Table
Digital Signal Processor Having Instruction Set With A Logarithm Function Using Reduced Look-Up Table
Receiver and Method for Estimating a Plurality of Estimated Transfer Functions Corresponding to Wireless Channels in a Multiple-Input System
Methods and Apparatus for System Framing Synchronization Control for a Framer/Mapper/Multiplexor Device with 1+1 and Equipment Protection
Branch Target Buffer with Entry Source Field for Use in Determining Replacement Priority
Systems and Methods for Processing Regular Expressions
System and Method of Xml Query Processing
Application:
12/407,706 →
Publication:
US 2009/0177960
Dct-Based Technique with Rhombus Scanning for Image Compression
Buffered Crossbar Switch System
Low Depth Programmable Priority Encoders
Controller and Method for Statistical Allocation of Multichannel Direct Memory Access Bandwidth
Scalable Packet-Switch
Method and Apparatus for Signal Formation with Guaranteed Consistent Overhead Insertion
Received Information Monitor Adaptive to Multiple Monitoring Modes in a Communication Device
Adaptive Filtering with Flexible Selection of Algorithm Complexity and Performance
Rapid Sampling Phase Recovery
N+1 Protection Using a Processor-Based Protection Device
Method and Apparatus for N+1 Packet Level Mesh Protection
Time-Slot Interchange Circuit
Bch or Reed-Solomon Decoder with Syndrome Modification
Adaptive Clock Recovery with Step-Delay Pre-Compensation
Three-Stage Architecture for Adaptive Clock Recovery
Windowing Technique for Adaptive Clock Recovery and Other Signal-Processing Applications
Network Communications Processor Architecture
Network Communications Processor Architecture with Memory Load Balancing
Task Queuing in a Network Communications Processor Architecture
Reducing a Degree of a Polynomial in a Polynomial Division Calculation
Impulse Regular Expression Matching
Fully Asynchronous Direct Memory Access Controller and Processor Work
Method and System for Parallel Computation of Linear Sequential Circuits
System and Method for Providing Memory Bandwidth Efficient Correlation Acceleration
Packet Sequence Number Tracking for an Anti-Replay Window
Avoiding Stall in Processor Pipeline Upon Read After Write Resource Conflict When Intervening Write Present
Adaptive Method and System of Regulation of Yellow Traffic in a Network
Methods and Apparatus for Linked-List Circular Buffer Management
Sequentially packing mask selected bits from plural words in circularly coupled register pair for transferring filled register bits to memory
Copying Data to a Cache Using Direct Memory Access
Low Depth Programmable Priority Encoders
Cache Prefetch Learning
Methods for Efficient State Transition Matrix Based Lfsr Computations
Multi-Destination Direct Memory Access Transfer
Method and Apparatus for Non-uniform Redundancy Packet Error Correction
Memory Manager for a Network Communications Processor Architecture
Time Synchronization Using Packet-Layer and Physical-Layer Protocols
Method and Apparatus for Caching Prefetched Data
Packet Assembly Module for Multi-Core, Multi-Thread Network Processors
Efficient Implementation of M-Algorithm Based on Qr Decomposition for Higher-Order Constellations
Thread Synchronization in a Multi-Thread Network Communications Processor Architecture
Reducing Data Read Latency in a Network Communications Processor Architecture
Thread Synchronization in a Multi-Thread Network Communications Processor Architecture
Instruction Breakpoints in a Multi-Core, Multi-Thread Network Communications Processor Architecture
Concurrent, Coherent Cache Access for Multiple Threads in a Multi-Core, Multi-Thread Network Processor
Security Protocol Processing for Anti-Replay Protection
Detection of Patterns in a Data Stream
Iterative-Division Operations Such as for Header Compression in Packet-Based Communications
Hash Processing in a Network Communications Processor Architecture
Hash Processing in a Network Communications Processor Architecture
Exception Detection and Thread Rescheduling in a Multi-Core, Multi-Thread Network Processor
System and Method for Split Ring First in First Out Buffer Memory with Priority
Securtiy Association Prefetch for Security Protcol Processing
System and Method of Speech Compression Using an Inter Frame Parameter Correlation
High-Performance Tone Detection Using a Digital Signal Processor (Dsp) Having Multiple Arithmetic Logic Units (Alus)
Representation of Data Relative to Varying Thresholds
Turbo Parallel Concatenated Convolutional Code Implementation on Multiple-Issue Processor Cores
Cache Replacement Using Active Cache Line Counters
Intra-Mode Prediction for a Video Transcoder
Motion Estimation for a Video Transcoder
Adjustment of Negative Weights in Weighted Round Robin Scheduling
Application:
13/165,852 →
Publication:
US 2012/0327948
Packet Reassembly Processing
Systems and Methods for Processing Regular Expressions
Data Caching in a Network Communications Processor Architecture
Dynamic Configuration of Processing Modules in a Network Communications Processor Architecture
Data Caching in a Network Communications Processor Architecture
Time-Domain Acoustic Echo Control
Skip Based Control Logic for First in First Out Buffer
Skip Based Control Logic for First in First Out Buffer
Low Depth Combinational Finite Field Multiplier
Multicasting Traffic Manager in a Network Communications Processor Architecture
Stochastic Vector Based Network Echo Cancellation
Orthogonal Variable Spreading Factor Code Sequence Generation
Methods and Apparatus for Search Sphere Linear Block Decoding
Packet Draining from a Scheduling Hierarchy in a Traffic Manager of a Network Processor
Speculative Task Reading in a Traffic Manager of a Network Processor
Packet Scheduling with Guaranteed Minimum Rate in a Traffic Manager of a Network Processor
Dynamic Updating of Scheduling Hierarchy in a Traffic Manager of a Network Processor
Local Messaging in a Scheduling Hierarchy in a Traffic Manager of a Network Processor
Scheduling Hierarchy in a Traffic Manager of a Network Processor
Byte-Accurate Scheduling in a Network Processor
Root Scheduling Algorithm in a Network Processor
Packet Draining from a Scheduling Hierarchy in a Traffic Manager of a Network Processor
Shared Task Parameters in a Scheduler of a Network Processor
Hybrid Address Mutex Mechanism for Memory Accesses in a Network Processor
Modularized Scheduling Engine for Traffic Management in a Network Processor
Multithreaded, Superscalar Scheduling in a Traffic Manager of a Network Processor
Configurable Memory Encryption with Constant Pipeline Delay in a Multi-Core Processor
Double Precision Approximation of a Single Precision Operation
Intra-Prediction Mode Selection While Encoding a Picture
Multiplication Dynamic Range Increase by on the Fly Data Scaling
Application:
13/292,377 →
Publication:
US 2013/0113543
Fast Echo Gain Change Detection
Cache Prefetch During Motion Estimation
Statistics Module for Network Processors in Virtual Local Area Networks
Tracking Written Addresses of a Shared Memory of a Multi-Core Processor
Implementation of Negation in a Multiplication Operation Without Post-Incrementation
Reframing Circuitry with Virtual Container Drop and Insert Functionality to Support Circuit Emulation Protocols
Biquad Infinite Impulse Response System Transformation
Multithreaded DFA architecture for finding rules match by concurrently performing at varying input stream positions and sorting result tokens
BEGIN ANCHOR ANNOTATION IN DFAs
Memory Manager for a Network Communications Processor Architecture
Low Access Time Indirect Memory Accesses
Concurrent Linked-List Traversal for Real-Time Hash Processing in Multi-Core, Multi-Thread Network Processors
Packet Assembly Module for Multi-Core, Multi-Thread Network Processors
On-Demand Allocation of Cache Memory for Use as a Preset Buffer
Methods and Apparatus for Efficient Tone Detection
Trend-Analysis Scheme for Reliably Reading Data Values from Memory
Method and Apparatus to Perform Floating Point Operations
Adjusting Direct Memory Access Transfers Used in Video Decoding
Efficient Extraction of Execution Sets from Fetch Sets
Efficient Application Recognition in Network Traffic
Controlling a Sequence of Parallel Executions
Application:
13/465,179 →
Publication:
US 2013/0298129
Compiled Control Code Parallelization by Hardware Treatment of Data Dependency
Application:
13/466,389 →
Publication:
US 2013/0305017
Multi-Threaded Processing with Hardware Accelerators
Memory Mapped Fetch-Ahead Control for Data Cache Accesses
Application:
13/478,561 →
Publication:
US 2013/0318307
Multicast Address Learning in an Input/Output Adapter of a Network Processor
Reliable Notification of Interrupts in a Network Processor by Prioritization and Policing of Interrupts
Timestamping Logic with Auto-Adjust for Varying System Frequencies
Patent:
8,598,910 →
Application:
13/565,083 →
Incremental Preamble Detection
Sharing of Internal Pipeline Resources of a Network Processor with External Devices
Mixed Radix Fast Hadamard Transform for Communication Systems
Method and Apparatus for N+1 Packet Level Mesh Protection
Receiver and Method for Estimating a Plurality of Estimated Transfer Functions Corresponding to Wireless Channels in a Multiple-Input System
Architecture and Implementation Method of Programmable Arithmetic Controller for Cryptographic Applications
Application:
13/628,554 →
Publication:
US 2013/0024668
Blended Match Mode Dfa Scanning
Start Pointer Tracking in Nfas
Time Synchronization Using Packet-Layer and Physical-Layer Protocols
CHILD STATE PRE-FETCH IN NFAs
Nfa Character Class Matching
Crest Factor Reduction (Cfr) Using Asymmetrical Pulses
Multi-Stage Crest Factor Reduction (Cfr) for Multi-Channel Multi-Standard Radio
Combined Rf Equalizer and I/Q Imbalance Correction
Recursive Digital Pre-Distortion (Dpd)
Method of Concealing Picture Header Errors in Digital Video Decoding
Application:
13/661,675 →
Publication:
US 2014/0119445
Detection of Double Talk in Telecommunications Networks
Cache Prefetch for Nfa Instructions
COMPLEX NFA STATE MATCHING METHOD THAT MATCHES INPUT SYMBOLS AGAINST CHARACTER CLASSES (CCLs), AND COMPARES SEQUENCE CCLs IN PARALLEL
Dfa-Nfa Hybrid
Thread Synchronization in a Multi-Thread, Multi-Flow Network Communications Processor Architecture
Task Queuing in a Multi-Flow Network Processor Architecture
Task Backpressure and Deletion in a Multi-Flow Network Processor Architecture
Changing a Flow Identifier of a Packet in a Multi-Thread, Multi-Flow Network Processor
Modifying Data Streams without Reordering in a Multi-Thread, Multi-Flow Network Processor
Early Cache Eviction in a Multi-Flow Network Processor Architecture
Dynamic Slice Resizing While Encoding Video
Direct Digital Synthesis Of Signals Using Maximum Likelihood Bit-Stream Encoding
Software Digital Front End (SoftDFE) Signal Processing
Vector Processor Having Instruction Set with Vector Convolution Function for Fir Filtering
Processor Having Instruction Set with User-Defined Non-Linear Functions for Digital Pre-Distortion (Dpd) and Other Non-Linear Applications
Application:
13/701,384 →
Publication:
US 2014/0086361
Digital Processor Having Instruction Set with Complex Exponential Non-Linear Function
Block-Based Crest Factor Reduction (Cfr)
Address Learning and Aging for Network Bridging in a Network Processor
Non-Deterministic Finite Automaton (Nfa) Overflow Recovery That Ejects an End of Scan Set of Active States into a Buffer
Multi-Layer Approach for Frame-Missing Concealment in a Video Decoder
Multiple Step Non-Deterministic Finite Automaton Matching
Cache Prefetch for Deterministic Finite Automaton Instructions
System and Method for Providing Fast and Efficient Flushing of a Forwarding Database in a Network Processor
Network Switch with External Buffering via Looparound Path
Hierarchical Self-Organizing Classification Processing in a Network Switch
Dfa Compression and Execution
Efficient Region of Interest Detection
Incremental Dfa Compilation with Single Rule Granularity
Dfa Sub-Scans
Application:
13/755,215 →
Publication:
US 2014/0215090
System and Method for Dfa-Nfa Splitting
Packet Data Processor in a Communications Processor Architecture
System and Method for De-Queuing an Active Queue
Application:
13/795,350 →
Publication:
US 2014/0258759
Network Processor Having Multicasting Protocol
Transmit Reference Signal Cleanup Within a Synchronous Network Application
Application:
13/796,153 →
Publication:
US 2014/0254735
Preamble Detection Using Vector Processors
Concurrent Linked-List Traversal for Real-Time Hash Processing in Multi-Core, Multi-Thread Network Processors
Switch Device With Device-Specified Bridge Domains
Application:
13/955,446 →
Publication:
US 2015/0030027
Dynamic Selection of Cache Levels
Application:
13/959,978 →
Publication:
US 2015/0032963
Method for Estimating a Plurality of Estimated Transfer Functions Corresponding to Wireless Channels in a Multiple-Input System
De-Interleaving on an as-Needed Basis
Maximum Likelihood Bit-Stream Generation and Detection Using M-Algorithm and Infinite Impulse Response Filtering
Low Complexity Tone/Voice Discrimination Method Using a Rising Edge of a Frequency Power Envelope
Impulse Regular Expression Matching
Multi-Core Architecture for Low Latency Video Decoder
Trend-Analysis Scheme for Reliably Reading Data Values from Memory
Application:
14/305,585 →
Publication:
US 2014/0298148
Dynamic Max Rate Control Algorithm for Available Bit Rate Service in Atm Networks
Application:
60/014,264 →
Method and Apparatus for Guaranteeing Data Transfer Rates and Delays in Asynchronous Transfer Mode Networks Using Single-Bit Timestamps
Application:
60/107,096 →
Plato Next Generation Interface
Application:
60/112,379 →
Method and Apparatus for Guaranteeing Data Transfer Rates and Delays in Asynchronous Transfer Mode Networks Using Pivot Sessions
Application:
60/137,542 →
Method and Apparatus for Providing Differentiated Quality-of-Service Guarantees in Scalable Packet Switches
Application:
60/168,989 →
Method and apparatus for guaranteeing data transfer rates and enforcing conformance with traffic profiles in a packet network
Application:
60/208,755 →
Voice payload processor
Application:
60/245,416 →
Buffer management for merging packets of virtual circuits
Application:
60/285,930 →
Bandwidth doubling of STS-1 switching elements
Application:
60/381,870 →
Large capacity switching system
Application:
60/387,394 →
Duobinary pulse shaping for PAM transmission over optical channels
Application:
60/412,870 →
Traffic management of packet-based applications
Application:
60/472,176 →
Virtual concatenation of PDH signals
Application:
60/658,945 →
PDV generation with a uniformly distributed PDF for packet timing recovery stress testing
Application:
60/904,646 →
Connectionless and connection-oriented test configurations evaluating adaptive packet timing recovery systems
Application:
60/904,652 →
Step-target delay approach to generating packet delay variation
Application:
60/904,728 →
Derivative PDV as a metric for use in packet-timing recovery stress training
Application:
60/904,835 →
Reducing Network Performance Degradation
Application:
60/915,013 →
N+1 Protection Using a Processor-Based Protection Device
Application:
61/162,409 →
Adaptive Clock Recovery
Application:
61/292,534 →
Hash Processing in a Multi-Thread Processing Engine
Application:
61/313,189 →
Thread Processing in a Multi-Thread Processing Engine
Application:
61/313,219 →
Memory Structures for Multi-Core, Multi-Thread Network Processors
Application:
61/313,399 →
Methods for Parallel Computation of Linear Sequential Circuits
Application:
61/355,177 →
Traffic Manager for Network Processor
Application:
61/388,962 →
Packet Assembly Module for Multi-Core, Multi-Thread Network Processors
Application:
61/412,019 →
Queue-based architecture for dynamic configuration of multiple engines and non-coherent system memory modules
Application:
61/421,243 →
Multithreaded System For Efficient Integration of Programmable Processor and Hardware Acceleration Engines
Application:
61/486,811 →
Software Digital Front End (SoftDFE) Signal Processing and Digital Radio
Application:
61/552,242 →
Task Ordering and Processing in a Network Processor
Application:
61/564,811 →
Multicast Address Learning in an Input/Output Adapter of a Network Processor
Application:
61/580,170 →
Sharing of Internal Pipeline Resources of a Network Processor with External Devices
Application:
61/580,183 →
Address Learning and Aging for Network Bridging in a Network Processor
Application:
61/580,219 →
Hierarchical Self-Organizing Classification Processing in a Network Switch
Application:
61/732,129 →
Optimized Caching for Packet Processing
Application:
61/732,171 →
System and Method for De-Queuing an Active Queue
Application:
61/773,412 →
Network Processor Having Multicasting Protocol
Application:
61/774,646 →
Transmit Reference Signal Cleanup Within a Synchronous Network Application
Application:
61/775,928 →
Switch Device With Device-Specified Bridge Domains
Application:
61/858,855 →
Dynamic Selection of Cache Levels
Application:
61/859,340 →
Multi-Core Architecture for Low Latency Video Decoder
Application:
61/929,640 →
Related Assignments
(21)
Other recorded transfers of the patents in this record — the chain of ownership.
Patent Security Agreement
May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Change of Name
Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
Assignment of Assignor's Interest
Oct 19, 2014
From: LUCENT TECHNOLOGIES INC.
To: AGERE SYSTEMS GUARDIAN CORP.
Reel/Frame 033977/0125 →
Assignment of Assignor's Interest
Oct 19, 2014
From: LUCENT TECHNOLOGIES INC.
To: AGERE SYSTEMS GUARDIAN CORP.
Reel/Frame 033977/0162 →
Merger
Oct 19, 2014
From: AGERE SYSTEMS GUARDIAN CORP.
To: AGERE SYSTEMS INC.
Reel/Frame 033977/0311 →
Change of Name
Oct 19, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033977/0397 →
Certificate of Conversion
Oct 19, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 034014/0846 →
Assignment of Assignor's Interest
Oct 19, 2014
From: AT&T CORP.
To: LUCENT TECHNOLOGIES INC.
Reel/Frame 033976/0835 →
Assignment of Assignor's Interest
Oct 19, 2014
From: LUCENT TECHNOLOGIES INC.
To: AGERE SYSTEMS GUARDIAN CORP.
Reel/Frame 033977/0001 →
Assignment of Assignor's Interest
Oct 27, 2014
From: LUCENT TECHNOLOGIES INC.
To: AGERE SYSTEMS GUARDIAN CORP.
Reel/Frame 034044/0222 →
Assignment of Assignor's Interest
Oct 30, 2014
From: LUCENT TECHNOLOGIES INC.
To: AGERE SYSTEMS GUARDIAN CORP.
Reel/Frame 034076/0405 →
Assignment of Assignor's Interest
Oct 30, 2014
From: LUCENT TECHNOLOGIES INC.
To: AGERE SYSTEMS GUARDIAN CORP.
Reel/Frame 034076/0291 →
Merger
Oct 30, 2014
From: AGERE SYSTEMS GUARDIAN CORP.
To: AGERE SYSTEMS INC.
Reel/Frame 034076/0459 →
Certificate of Conversion
Oct 30, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 034113/0626 →
Assignment of Assignor's Interest
Nov 10, 2014
From: AT&T CORP.
To: LUCENT TECHNOLOGIES INC.
Reel/Frame 034139/0265 →
Merger
Nov 10, 2014
From: AGERE SYSTEMS GUARDIAN CORP.
To: AGERE SYSTEMS INC.
Reel/Frame 034139/0497 →
Certificate of Conversion
Nov 10, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 034197/0271 →
Assignment of Assignor's Interest
Nov 10, 2014
From: LUCENT TECHNOLOGIES INC.
To: AGERE SYSTEMS GUARDIAN CORP.
Reel/Frame 034139/0411 →
Assignment of Assignor's Interest
Nov 14, 2014
From: AGERE SYSTEMS LLC
To: LSI CORPORATION
Reel/Frame 034245/0655 →
Termination and Release of Security Interest in Patents at Reel/Frame No. 32856/0031
Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032856-0031)
Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →