Multi-protocol bus system and method of operation thereof
View Patent ↗A multi-protocol bus system and a method of operating the same. In one embodiment, the multi-protocol bus system includes a plurality of protocol indicators associated with an address space, each of the plurality of protocol indicators associated with a segment of the address space and configured to indicate a particular bus protocol. The multi-protocol bus system further includes a bus protocol selection subsystem configured to employ control lines to implement one of the particular bus protocols in accordance with a selected one of the protocol indicators based upon an addressed segment of the address space.
1. A multi-protocol bus system, comprising:
a plurality of protocol indicators associated with an address space, each of said plurality of protocol indicators associated with a segment of said address space and configured to indicate a particular bus protocol employed to communicate with an external device; and
a bus protocol selection subsystem configured to employ control lines to implement one of said particular bus protocols in accordance with a selected one of said protocol indicators based upon an addressed segment of said address space.
2. The multi-protocol bus system as recited in claim 1 further comprising a chip selection subsystem configured to provide a chip selection signal to an external device based upon said addressed segment of said address space.
3. The multi-protocol bus system as recited in claim 2 wherein said external device is selected from the group consisting of:
a fast pattern processor,
a routing switch processor,
a Motorola-style bus architecture device, and
an Intel-style bus architecture device.
4. The multi-protocol bus system as recited in claim 1 wherein said particular bus protocol is selected from the group consisting of:
a Motorola-style bus protocol, and
an Intel-style bus protocol.
5. The multi-protocol bus system as recited in claim 1 wherein said control lines are selected from the group consisting of:
an address latch enable control line,
a chip select control line,
a read data strobe control line,
a write data strobe control line,
a ready control line,
a read/write select control line,
a data strobe control line, and
a data acknowledge control line.
6. The multi-protocol bus system as recited in claim 1 wherein each segment of said address space is four kilobytes.
7. The multi-protocol bus system as recited in claim 1 wherein said address space is a peripheral component interconnect (PCI) address space of thirty-two kilobytes.
8. A method of operating a multi-protocol bus system, comprising:
employing a plurality of protocol indicators associated with an address space, each of said plurality of protocol indicators associated with a segment of said address space and indicate a particular bus protocol employed to communicate with an external device; and
employing control lines to implement one of said particular bus protocols in accordance with a selected one of said protocol indicators based upon an addressed segment of said address space.
9. The method as recited in claim 8 further comprising providing a chip selection signal to an external device with a chip selection subsystem based upon said addressed segment of said address space.
10. The method as recited in claim 9 wherein said external device is selected from the group consisting of:
a fast pattern processor,
a routing switch processor,
a Motorola-style bus architecture device, and
an Intel-style bus architecture device.
11. The method as recited in claim 8 wherein said particular bus protocol is selected from the group consisting of:
a Motorola-style bus protocol, and
an Intel-style bus protocol.
12. The method as recited in claim 8 wherein said control lines are selected from the group consisting of:
an address latch enable control line,
a chip select control line,
a read control line,
a write control line,
a ready control line,
a read/write control line,
a data strobe control line, and
a data acknowledge control line.
13. The method as recited in claim 8 wherein each segment of said address space is four kilobytes.
14. The method as recited in claim 8 wherein said address space is a peripheral component interconnect (PCI) address space of thirty-two kilobytes.
15. A method of operating a multi-protocol bus system, comprising:
dividing an address space into segments;
assigning at least one of said segments to an external device;
assigning a protocol indicator to said at least one of said segments, said protocol indicator representing a protocol to be employed when communicating with said external device;
determining if said at least one of said segments has been addressed;
retrieving said protocol indicator when said at least one of said segments has been addressed; and
implementing said protocol to communicate with said external device.