Patent Assignment
Reel/Frame 034113/0626
Certificate of Conversion
Recorded: 2014-10-30
Pages: 5
Assignor
AGERE SYSTEMS INC.
Executed: 2012-07-30
Assignee
AGERE SYSTEMS LLC
1110 AMERICAN PARKWAY NE, ALLENTOWN, PENNSYLVANIA, 18109
Covered Properties
(48)
Method and Apparatus for Reducing Data Delay Within a Multi-Channel Shared-Circuit Data Processing Environment
Patent:
5,790,072 →
Application:
08/537,568 →
Method and Apparatus for Reducing Noise in Speech and Audio Signals
Patent:
6,035,048 →
Application:
08/877,909 →
Multiple Tone Detection Using Out-of-Band Background Detector
Patent:
6,128,370 →
Application:
08/906,818 →
Method and Apparatus for Synchronizing Digital Speech Communications
Patent:
5,953,695 →
Application:
08/959,888 →
Echo Canceler Including Subband Echo Suppressor
Patent:
6,442,275 →
Application:
09/154,991 →
Mixed-Mode Next/Echo Canceller for Pulse Amplitude Modulated (Pam) Signals
Patent:
6,584,159 →
Application:
09/188,625 →
Second Order Lms Tap Update Algorithm with High Tracking Capability
Patent:
6,202,075 →
Application:
09/206,519 →
Method for Designing All Pass Digital Filters
Patent:
6,526,429 →
Application:
09/549,753 →
Multi-Protocol Bus System and Method of Operation Thereof
Patent:
6,925,514 →
Application:
09/821,892 →
System and Method for Updating Filter Coefficients and Echo Canceller Including Same
Voice Packet Processor and Method of Operation Thereof
Memory System for Increased Bandwidth
Method for Implementing Dual Link List Structure to Enable Fast Link-List Pointer Updates
Method of Improving the Lookup Performance of Tree-Type Knowledge Base Searches
Method and Apparatus for Providing Multiple Data Class Differentiation with Priorities Using a Single Scheduling Structure
Adaptive Threshold Based Jitter Buffer Management for Packetized Data
Low Power Vector Summation Method and Apparatus
Duobinary Pulse Shaping for Optical Transmission Systems Employing Pulse Amplitude Modulation Techniques
Real Time Tuner for Providing Graphical User Interface
Simulation Framework with Support for Multiple Integrated Circuits Having Potentially Differing Characteristics
Method and System for Wireless Communication with an Integrated Circuit Under Evaluation
Processor with Instruction-Based Interrupt Handling
Frame Mapping Scheduler for Scheduling Data Blocks Using a Mapping Table and a Weight Table
Frame Mapping Scheduler with Compressed Mapping Table
Adaptive Peak Windowing for Crest Factor Reduction in a Communication System Transmitter
Multi-Protocol Bus System and Method of Operation Thereof
Method for Encoding/Decoding a Binary Signal State in a Fault Tolerant Environment
Low Power Vector Summation Apparatus
Flexible Traffic Management and Shaping Processing for Multimedia Distribution
High-Throughput Scheduler with Guaranteed Fairness for Wireless Networks and Other Applications
Wireless Network Scheduling Methods and Apparatus Based on Both Waiting Time and Occupancy
Video Processing Architecture Having Reduced Memory Requirement
Methods and Apparatus for Controlling Latency Variation in a Packet Transfer Network
Methods and Apparatus for Testing Adaptive Timing Characteristics of Packet-Based Timing Protocol
Methods and Apparatus for Performing Reduced Complexity Discrete Fourier Transforms Using Interpolation
Adaptive Algorithm for Reducing Channel Zapping Time in Multicast Media
Method and System for Generating Packet Delay Variation with a Uniform Distribution
Derivative Packet Delay Variation as a Metric for Packet Timing Recovery Stress Testing
Simulating Packet Delay Variation Using Step-Target Delay Method
Connectionless Configurations for Stress Testing Timing and Synchronization in Data Packet Networks
Method and Apparatus for Simulating Packet Delay Variation of a Multi-Switch Network
Methods and Appratus for Evaluating a Utilization of a System That Provides Connections Using a Normalized Bandwidth Scheme
Methods and Apparatus for Improved Phase Linearity in a Multi-Phase Based Clock/Timing Recovery System
Digital Signal Processor Having Instruction Set With One Or More Non-Linear Complex Functions
Digital Signal Processor Having Instruction Set with One or More Non-Linear Functions Using Reduced Look-Up Table
Digital Signal Processor Having Instruction Set with One or More Non-Linear Functions Using Reduced Look-Up Table with Exponentially Varying Step-Size
Digital Signal Processor With One Or More Non-Linear Functions Using Factorized Polynomial Interpolation
Branch Target Buffer with Entry Source Field for Use in Determining Replacement Priority
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Patent Security Agreement
May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
Assignment of Assignor's Interest
Nov 14, 2014
From: AGERE SYSTEMS LLC
To: LSI CORPORATION
Reel/Frame 034245/0655 →
Termination and Release of Security Interest in Patents at Reel/Frame No. 32856/0031
Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
Assignment of Assignor's Interest
Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
Assignment of Assignor's Interest
Apr 3, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035365/0634 →
Termination and Release of Security Interest in Patent Rights (Releases Rf 032856-0031)
Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →