Multi-protocol bus system and method of operation thereof
View Patent ↗A multi-protocol bus system and a method of operating the same. In one embodiment, the multi-protocol bus system includes a plurality of protocol indicators associated with an address space, each of the plurality of protocol indicators associated with a segment of the address space and configured to indicate a particular bus protocol. The multi-protocol bus system further includes a bus protocol selection subsystem configured to employ control lines to implement one of the particular bus protocols in accordance with a selected one of the protocol indicators based upon an addressed segment of the address space.
1. A system interface processor, comprising:
a protocol data unit (PDU) receiver that receives PDUs;
a protocol data unit (PDU) transmitter that transmits PDUs; and
a peripheral component interconnect (PCI) interface that receives PDUs from said PDU receiver, transmits PDUs to said PDU transmitter and interfaces with a multi-protocol bus, said PCI interface including a multi-protocol bus system, having:
a plurality of protocol indicators associated with an address space, each of said plurality of protocol indicators associated with a segment of said address space and indicate a particular bus protocol; and
a bus protocol selection subsystem that employs control lines to implement one of said particular bus protocols in accordance with a selected one of said protocol indicators based upon an addressed segment of said address space.
2. The system interface processor as recited in claim 1 wherein said multi-protocol bus system further includes a chip selection subsystem that provides a chip selection signal to an external device based upon said addressed segment of said address space.
3. The system interface processor as recited in claim 2 wherein said external device is selected from the group consisting of:
a fast pattern processor,
a routing switch processor,
a Motorola-style bus architecture device, and
an Intel-style bus architecture device.
4. The system interface processor as recited in claim 1 wherein said particular bus protocol is selected from the group consisting of:
a Motorola-style bus protocol, and
an Intel-style bus protocol.
5. The system interface processor as recited in claim 1 wherein said control lines are selected from the group consisting of:
an address latch enable control line,
a chip select control line,
a read control line,
a write control line,
a ready control line,
a read/write control line,
a data strobe control line, and
a data acknowledge control line.
6. The system interface processor as recited in claim 1 wherein each segment of said address space is four kilobytes.
7. The system interface processor as recited in claim 1 wherein said address space is a peripheral component interconnect (PCI) address space of thirty-two kilobytes.