Digital signal processor with one or more non-linear functions using factorized polynomial interpolation
View Patent ↗A digital signal processor and method are disclosed with one or more non-linear functions using factorized polynomial interpolation. A digital signal processor evaluates a non-linear function for a value, x, by obtaining two or more values from at least one look-up table for said non-linear function that are near said value, x; and interpolating said two or more obtained values to obtain a value, y, using a factorized polynomial interpolation.
1. A method performed by a vector-based digital signal processor for evaluating a non-linear function for a vector, x, comprising:
in response to a predefined software instruction keyword for said non-linear function, performing the following steps, wherein said vector, x, comprises a plurality of numbers and wherein said vector-based digital signal processor processes said plurality of numbers substantially simultaneously, wherein said predefined software instruction keyword for said non-linear function is part of an instruction set of said vector-based digital signal processor:
invoking at least one non-linear hardware functional unit that implements said non-linear function, wherein said at least one non-linear hardware functional unit is configured to perform the following steps for each component of said vector, x, using hardware:
obtaining at least two sets of values from at least one look-up table for said non-linear function that are near components of said vector, x, wherein said at least one look-up table is in a random access memory (RAM) of said vector-based digital signal processor; and
interpolating said at least two obtained sets of values to obtain a vector result, y, using a factorized polynomial interpolation.
2. The method of claim 1 , further comprising the step of performing a modulo arithmetic operation for a periodic non-linear function.
3. The method of claim 1 , wherein said vector-based digital signal processor executes said predefined software instruction keyword from program code.
4. The method of claim 1 , wherein said at least one look-up table stores a subset of values for said non-linear function.
5. The method of claim 1 , wherein said factorized polynomial interpolation comprises a Taylor series.
6. The method of claim 1 , wherein said factorized polynomial interpolation comprises a Horner scheme.
7. The method of claim 1 , wherein said vector-based digital signal processor employs one or more of hardware and a look-up table to compute the vector result, y.
8. The method of claim 1 , wherein said non-linear function comprises one or more of a sine function, a cosine function, a logarithmic function, an exponent function and a square root function.
9. A vector-based digital signal processor for evaluating a non-linear function for a vector, x, comprising:
at least one non-linear hardware functional unit that implements said non-linear function, wherein said at least one non-linear hardware functional unit is invoked by said vector-based digital signal processor in response to a predefined software instruction keyword for said non-linear function, wherein said at least one non-linear hardware functional unit is configured to perform the following steps using hardware, wherein said vector, x, comprises a plurality of numbers and wherein said vector-based digital signal processor processes said plurality of numbers substantially simultaneously, wherein said predefined software instruction keyword for said non-linear function is part of an instruction set of said vector-based digital signal processor:
obtain at least two sets of values from at least one look-up table that stores a subset of values for said non-linear function, wherein said obtained at least two sets of values are near components of said vector, x, wherein said at least one look-up table is in a random access memory (RAM) of said vector-based digital signal processor; and
interpolate said at least two sets of values obtained from said at least one look-up table to obtain a vector result, y, using a factorized polynomial interpolation.
10. The vector-based digital signal processor of claim 9 , wherein said at least one non-linear hardware functional unit is further configured to perform further comprising a modulo arithmetic operation for a periodic non-linear function.
11. The vector-based digital signal processor of claim 9 , wherein said vector-based digital signal processor executes said predefined software instruction keyword from program code.
12. The vector-based digital signal processor of claim 9 , wherein said factorized polynomial interpolation comprises a Horner scheme.
13. The vector-based digital signal processor of claim 9 , wherein said vector-based digital signal processor employs one or more of hardware and a look-up table to compute the vector result, y.
14. The vector-based digital signal processor of claim 9 , wherein said non-linear function comprises one or more of a sine function, a cosine function, a logarithmic function, an exponent function and a square root function.
15. An integrated circuit, comprising:
a vector-based digital signal processor for evaluating a non-linear function for a vector, x, comprising:
at least one non-linear hardware functional unit that implements said non-linear function, wherein said non-linear hardware functional unit is invoked by said vector-based digital signal processor in response to a predefined software instruction keyword for said non-linear function, wherein said at least one non-linear hardware functional unit is configured to perform the following steps using hardware, wherein said vector, x, comprises a plurality of numbers and wherein said vector-based digital signal processor processes said plurality of numbers substantially simultaneously, wherein said predefined software instruction keyword for said non-linear function is part of an instruction set of said vector-based digital signal processor:
obtain at least two sets of values from at least one look-up table that stores a subset of values for a said non-linear function, wherein said obtained at least two sets of values are near components of said vector, x, wherein said at least one look-up table is in a random access memory (RAM) of said vector-based digital signal processor; and
interpolate said at least two sets of values obtained from said at least one look-up table to obtain a vector result, y, using a factorized polynomial interpolation.
16. The integrated circuit of claim 15 , wherein said at least one non-linear hardware functional unit is further configured to perform a modulo arithmetic operation for a periodic non-linear function.
17. The integrated circuit of claim 15 , wherein said vector-based digital signal processor executes said predefined software instruction keyword from program code.
18. The integrated circuit of claim 15 , wherein said factorized polynomial interpolation comprises a Horner scheme.
19. The integrated circuit of claim 15 , wherein said vector-based digital signal processor employs one or more of hardware and a look-up table to compute the vector result, y.
20. The integrated circuit of claim 15 , wherein said non-linear function comprises one or more of a sine function, a cosine function, a logarithmic function, an exponent function and a square root function.