IP Library Granted Patent US 7,873,506
Granted Patent B2
US 7,873,506 · App. 10/609,781 · Granted Jan 18, 2011

Simulation framework with support for multiple integrated circuits having potentially differing characteristics

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Quick Facts
Patent No.
US 7,873,506
App. No.
10/609,781
Granted
Jan 18, 2011
Kind
B2
Abstract

The operation of an electronic system comprising a plurality of integrated circuits or other circuit elements is simulated using a software-based development tool that provides a generic framework for simultaneous simulation of multiple circuit elements having potentially different clock speeds, latencies or other characteristics. One or more interfaces provided in the software-based development tool permit registration of processing events associated with one or more of the circuit elements. The software-based development tool is further operative to determine a system clock for a given simulation, and to schedule execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks, so as to maintain consistency in the execution of the processing events relative to the determined system clock.

Claims (34)

1. A method of simulating the operation of an electronic system comprising a plurality of circuit elements, utilizing a software-based development tool, the method comprising the steps of:

providing in the software-based development tool an interface permitting registration of processing events associated with one or more of the plurality of circuit elements;

determining a system clock for a given simulation;

scheduling execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks so as to maintain consistency in the execution of the processing events relative to the determined system clock; and

executing the processing events in the manner determined in the scheduling step to simulate the operation of the electronic system;

wherein the software-based development tool stores for the circuit elements respective indications of previously unscheduled clock cycles and such clock cycles are automatically run in conjunction with execution of corresponding ones of the processing events.

2. The method of claim 1 wherein at least a subset of the circuit elements each comprise one or more integrated circuits.

3. The method of claim 1 wherein at least one of the plurality of circuit elements has a clock speed that differs from that of at least another one of the circuit elements.

4. The method of claim 1 wherein at least one of the plurality of circuit elements has a processing event latency that differs from that of at least another one of the circuit elements.

5. The method of claim 1 wherein the software-based development tool runs at least in part on an information processing device comprising a processor and an associated memory.

6. The method of claim 1 wherein the software-based development tool comprises a simulator control module, a set of interfaces, and circuit element modules each corresponding to an associated one of the circuit elements.

7. The method of claim 6 wherein the simulator control module comprises an event scheduler module.

8. The method of claim 6 wherein the set of interfaces comprises a simulator runtime interface shared by the plurality of circuit element modules and a separate circuit element interface for each of the circuit element modules.

9. The method of claim 8 wherein the simulator runtime interface comprises one or more Service Provider Interfaces (SPIs) each specifying one or more entry points for the associated processing events.

10. The method of claim 6 wherein each of the circuit element modules comprises a plurality of clock-based block functions executable in conjunction with the given simulation.

11. The method of claim 6 wherein the set of interfaces comprises, for at least a given one of the circuit element modules, an event interface between the circuit element module and an event scheduler associated with the simulator control module.

12. The method of claim 6 wherein the set of interfaces comprises, for at least a given one of the circuit element modules, a connection interface between the circuit element module and one or more corresponding interfaces associated with one or more of the other circuit element modules.

13. The method of claim 1 wherein at least one of the circuit elements comprises a plug-in circuit element associated with an entity other than an entity associated with one or more of the other circuit elements.

14. The method of claim 1 wherein information characterizing the associated processing events of one or more of the circuit elements is defined at least in part utilizing extensible markup language (XML) in a manner that facilitates the loading of such information into the software-based development tool.

15. The method of claim 1 wherein the step of determining a system clock for a given simulation further comprises determining the system clock as a clock having the highest clock speed among clock speeds of the plurality of circuit elements.

16. The method of claim 1 wherein circuit element modules corresponding to the respective circuit elements are configured to query a simulator control module for information regarding a number of cycles of a circuit element clock associated with a given state of the system clock.

17. The method of claim 1 wherein a current global clock based on the determined system clock is monitored relative to one or more circuit element clocks.

18. The method of claim 1 wherein unscheduled cycles of one or more circuit element clocks are determined and a simulator control module invokes entry points into associated circuit element modules to run one or more of the unscheduled cycles.

19. An apparatus for simulating the operation of an electronic system comprising a plurality of circuit elements, the apparatus comprising:

an information processing device having a processor and a memory;

the information processing device implementing a software-based development tool providing an interface permitting registration of processing events associated with one or more of the plurality of circuit elements;

wherein the software-based development tool is further operative to determine a system clock for a given simulation, to schedule execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks so as to maintain consistency in the execution of the processing events relative to the determined system clock, and to execute the processing events in accordance with the schedule to simulate the operation of the electronic system; and

wherein the software-based development tool stores for the circuit elements respective indications of previously unscheduled clock cycles and such clock cycles are automatically run in conjunction with execution of corresponding ones of the processing events.

20. An article of manufacture comprising a storage medium containing one or more software programs for use in simulating the operation of an electronic system comprising a plurality of circuit elements, utilizing a software-based development tool, wherein the one or more software programs when executed implement the steps of:

providing in the software-based development tool an interface permitting registration of processing events associated with one or more of the plurality of circuit elements;

determining a system clock for a given simulation; and

scheduling execution of the associated processing events in a manner that takes into account differences between the system clock and one or more circuit element clocks so as to maintain consistency in the execution of the processing events relative to the determined system clock; and

executing the processing events in the manner determined in the scheduling step to simulate the operation of the electronic system;

wherein the software-based development tool stores for the circuit elements respective indications of previously unscheduled clock cycles and such clock cycles are automatically run in conjunction with execution of corresponding ones of the processing events.

Assignments (7)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2015
From: LSI CORPORATION
To: INTEL CORPORATION
Reel/Frame 035090/0477 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS AT REEL/FRAME NO. 32856/0031 Recorded Nov 18, 2014
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 034286/0872 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2014
From: AGERE SYSTEMS LLC
To: LSI CORPORATION
Reel/Frame 034245/0655 →
CERTIFICATE OF CONVERSION Recorded Oct 30, 2014
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 034113/0626 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 21, 2003
From: HINTIKKA, PAUL N.; KASSA, SILESHI; KUMAR, VINOJ N.; MANDAVA, RAVI K.
To: AGERE SYSTEMS INC.
Reel/Frame 014742/0551 →