Granted Patent B2

US 9,069,686 · App. 12/324,931 · Granted Jun 30, 2015

Abstract

Claims (33)

1. A method performed by a vector-based digital signal processor for evaluating a non-linear function for a vector, x, comprising:

receiving the vector, x, the vector including scalar numbers, an identifier and a parameter for the non-linear function;

in response to a predefined software instruction keyword for said non-linear function, the vector-based digital signal processor processes the scalar numbers simultaneously by:

invoking at least one hardware non-linear functional unit that implements said non-linear function, wherein said at least one hardware non-linear functional unit is configured to perform the following steps:

obtaining at least two sets of values from at least one look-up table for said non-linear function that are near each scalar number of said vector, x, wherein said at least one look-up table stores a subset of values for said non-linear function using exponentially-varying step sizes; and

interpolating said at least two obtained values to obtain a vector result, y, wherein said predefined software instruction keyword for said non-linear function is part of an instruction set of said vector-based digital signal processor.

2. The method of claim 1 , further comprising the step of using a position of one or more leading zeros in said scalar numbers to access said at least one look-up table.

3. The method of claim 1 , wherein said interpolating step comprises a linear interpolation.

4. The method of claim 1 , wherein said interpolating step comprises a polynomial interpolation.

5. The method of claim 1 , further comprising a modulo arithmetic operation for a periodic non-linear function.

6. The method of claim 1 , wherein said vector-based digital signal processor executes said predefined software instruction keyword from program code.

7. A vector-based digital signal processor, comprising:

a circuitry to receive a vector including a set of scalar numbers, an identifier and a parameter for a non-linear function;

at least one hardware non-linear functional unit that implements a non-linear function, wherein said hardware non-linear functional unit is invoked by said vector-based digital signal processor in response to a predefined software instruction keyword for said non-linear function, wherein said at least one hardware non-linear functional unit is configured to:

obtain at least two values from at least one look-up table, the at least two values near each scalar number of said vector, x, wherein said at least one look-up table stores a subset of values for said non-linear function using exponentially-varying step sizes; and

interpolate said at least two values obtained from said at least one look-up table to obtain a vector result, y, wherein said predefined software instruction keyword for said non-linear function is part of an instruction set of said vector-based digital signal processor, wherein the set of scalar numbers are simultaneously processed by said at least one hardware non-linear functional unit.

8. The vector-based digital signal processor of claim 7 , wherein a position of one or more leading zeros in said scalar numbers are used to access said at least one look-up table.

9. The vector-based digital signal processor of claim 7 , wherein said hardware non-linear functional unit performs a linear interpolation.

10. The vector-based digital signal processor of claim 7 , wherein said hardware non-linear functional unit performs a polynomial interpolation.

11. The vector-based digital signal processor of claim 7 , further comprising a modulo arithmetic operation for a periodic non-linear function.

12. The vector-based digital signal processor of claim 7 , wherein said vector-based digital signal processor executes said predefined software instruction keyword from program code.

13. An integrated circuit, comprising:

a vector-based digital signal processor for evaluating a non-linear function for a vector, x, the vector including scalar numbers, an identifier and a parameter for the non-linear function, the vector-based digital signal processor, comprising:

at least one hardware non-linear functional unit that implements a non-linear function, wherein said at least one hardware non-linear functional unit is invoked by said vector-based digital signal processor in response to a predefined software instruction keyword for said non-linear function, wherein said at least one hardware non-linear functional unit is configured to simultaneously:

obtain at least two values from at least one look-up table near each scalar number of said vector, x, wherein said at least look-up table stores a subset of values for a non-linear function using exponentially-varying step sizes; and

an interpolator that interpolates at least two values obtained from said at least one look-up table to obtain a result.

14. The integrated circuit of claim 13 , wherein a position of one or more leading zeros in said scalar numbers are used to access said at least one look-up table.

15. The integrated circuit of claim 13 , wherein said interpolator performs a linear interpolation.

16. The integrated circuit of claim 13 , wherein said interpolator performs a polynomial interpolation.

17. The integrated circuit of claim 13 , further comprising a modulo arithmetic operation for a periodic non-linear function.

18. The integrated circuit of claim 13 , wherein said digital signal processor executes software instructions from program code.

19. The method of claim 1 , wherein the parameter defines a period for periodic non-linear functions.

20. The method of claim 1 , wherein the parameter includes a value of zero that defines a non-periodic and non-linear function.

Assignments (7)