Methods and apparatus for controlling latency variation in a packet transfer network
View Patent ↗Methods and apparatus for controlling latency variation of packets received in a packet transfer network are provided. A plurality of packets is received at a network element of a receive node of the packet transfer network. A time-stamp is provided for each of the plurality of packets. An egress delay time is computed at a scheduler of the network element for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression from the network element.
1. A method for controlling latency variation of packets received in a packet transfer network comprising the steps of:
receiving a plurality of packets at a network element of a receive node of the packet transfer network;
providing a time-stamp for each of the plurality of packets; and
computing an egress delay time at a scheduler of the network element for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression from the network element;
wherein the egress delay time is computed as a function of the substantially constant latency and a difference between the corresponding time-stamp and a second time-stamp; and
wherein the substantially constant latency comprises a constant regular interval.
2. The method of claim 1 , further comprising the step of queuing each of the plurality of packets for egression from the network element.
3. The method of claim 1 , further comprising the step of classifying each of the plurality of packets received at the network element in accordance with a nature of each of the plurality of packets.
4. The method of claim 1 , wherein, in the step of providing a time-stamp, the time-stamp is provided in accordance with a real-time clock of the network element.
5. The method of claim 1 , further comprising the step of transmitting each of the plurality of packets through an egress port in accordance with each corresponding egress delay time computed at the scheduler.
6. The method of claim 1 , wherein, in the step of receiving a plurality of packets, the plurality of packets are received at an ingress port of the network element.
7. The method of claim 1 , wherein the network element comprises at least one of a router, a switch, and a multiplexer.
8. The method of claim 1 , wherein, in the step of computing an egress delay time, the egress delay time is computed in accordance with the equation dT=I−(TS 0 −TS i )−T 0 , where dT is the egress delay time, I is the constant regular interval, TS 0 is the second time-stamp, TS i is the corresponding time-stamp, and T 0 is a maximum intrinsic delay.
9. A computer-readable storage medium having executable code embodied therein for controlling latency variation of packets received in a packet transfer network, said executable code comprising one or more programs which when executed implement the steps of claim 1 .
10. Apparatus for controlling latency variation of packets received in a packet transfer network, comprising:
a memory; and
at least one processor coupled to the memory and operative to: (i) receive a plurality of packets at a network element of a receive node of the packet transfer network; (ii) provide a time-stamp for each of the plurality of packets; and (iii) compute an egress delay time at a scheduler of the network element for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression from the network element;
wherein the egress delay time is computed as a function of a plurality of the substantially constant latency and a difference between the corresponding time-stamp and a second time-stamp; and
wherein the substantially constant latency comprises a constant regular interval.
11. The apparatus of claim 10 , wherein the at least one processor is further operative to queue each of the plurality of packets for egression from the network element.
12. The apparatus of claim 10 , wherein the at least one processor is further operative to classify each of the plurality of packets received at the network element in accordance with a nature of each of the plurality of packets.
13. The apparatus of claim 10 , wherein the time-stamp is provided in accordance with a real-time clock of the network element.
14. The apparatus of claim 10 , wherein the at least one processor is further operative to transmit each of the plurality of packets through an egress port in accordance with each corresponding egress delay time computed at the scheduler.
15. The apparatus of claim 10 , wherein the plurality of packets are received at an ingress port of the network element.
16. A network element in a receive node of a packet transfer network comprising:
a classifier that provides a time-stamp for each of a plurality of packets received by the network element; and
a scheduler in communication with the classifier that computes an egress delay time for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression from the network element;
wherein the egress delay time is computed as a function of the substantially constant latency and a difference between the corresponding time-stamp and a second time-stamp; and
wherein the substantially constant latency comprises a constant regular interval.
17. The network element of claim 16 , further comprising a real-time clock in communication with the classifier for providing a time-stamp for each of the plurality of packets.
18. The network element of claim 16 , further comprising one or more queues in communication with the classifier and the scheduler that store one or more of the plurality of packets for egression from the network element.
19. The network element of claim 16 , further comprising an ingress port that is in communication with the classifier, and that receives each of the plurality of packets.
20. The network element of claim 16 , further comprising an egress port that is in communication with the scheduler, and through which each of the plurality of packets are transmitted in accordance with each corresponding egress delay time computed at the scheduler.
21. An integrated circuit device in a receive node for controlling latency variation of packets received in a packet transfer network, wherein the integrated circuit device is configured to: (i) receive a plurality of packets; (ii) provide a time-stamp for each of the plurality of packets; and (iii) compute an egress delay time for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression;
wherein the egress delay time is computed as a function of a plurality of the substantially constant latency and a difference between the corresponding time-stamp and a second time-stamp; and
wherein the substantially constant latency comprises a constant regular interval.
22. A packet transfer system comprising:
a transmit node; and
a receive node comprising:
a classifier that provides a time-stamp for each of a plurality of packets received by the network element; and
a scheduler in communication with the classifier that computes an egress delay time for each of the plurality of packets in accordance with each corresponding time-stamp to provide a substantially constant latency for the plurality of packets upon egression from the network element;
wherein the egress delay time is computed as a function of the substantially constant latency and a difference between the corresponding time-stamp and a second time-stamp; and
wherein the substantially constant latency comprises a constant regular interval.