Methods and apparatus for improved phase linearity in a multi-phase based clock/timing recovery system
View Patent ↗Methods and apparatus are provided for improved phase linearity in a multi-phase based clock/timing recovery system. Averaging and interpolation techniques improve phase linearity in a multi-phase clock system. A multi-phase output clock is generated in accordance with one aspect of the invention by generating a plurality of clocks each having a substantially similar frequency and a different phase; applying each of the plurality of clocks to at least one corresponding amplifier such as a differential pair circuit; and summing an output of the corresponding amplifiers to generate the multi-phase output clock. A multiple-stage averaging operation can provide further linearity improvements.
1. A method for generating a multi-phase output clock, comprising:
generating a plurality of clocks each having a substantially similar frequency and a different phase;
applying each of said plurality of clocks to at least one of a plurality of corresponding amplifiers;
summing an output of a first set of said plurality of corresponding amplifiers to generate a first phase of said multi-phase output clock; and
summing an output of a second set of said plurality of corresponding amplifiers to generate a second phase of said multi-phase output clock.
2. The method of claim 1 , wherein said generating step is performed by a ring oscillator.
3. The method of claim 1 , wherein each of said corresponding amplifiers comprises a differential pair circuit.
4. The method of claim 3 , wherein said summing step is performed by applying an output of said differential pair circuits to a load.
5. The method of claim 1 , further comprising the step of performing a multiple-stage averaging operation.
6. The method of claim 5 , wherein said multiple-stage averaging operation comprises applying said multi-phase output clock to at least a second set of corresponding amplifiers.
7. The method of claim 1 , wherein a phase of said multi-phase output clock is adjusted based on a phase selection control signal.
8. The method of claim 7 , wherein a rise/fall time of said phase selection control signal is longer than a frequency of said multi-phase output clock.
9. A clock generation circuit for generating a multi-phase output clock, comprising:
a ring oscillator generating a plurality of clocks having a substantially similar frequency and different phases;
a plurality of amplifiers, each of said amplifiers amplifying two or more of said plurality of clocks;
a first adder for summing an output of a first set of said plurality of amplifiers to generate a first phase of said multi-phase output clock; and
a second adder for summing an output of a second set of said plurality of amplifiers to generate a second phase of said multi-phase output clock.
10. The clock generation circuit of claim 9 , wherein each of said plurality of amplifiers comprises a differential pair circuit.
11. The clock generation circuit of claim 10 , wherein said adder comprises the application of an output of said differential pair circuits to a load.
12. The clock generation circuit of claim 9 , further comprising a plurality of averaging stages.
13. The clock generation circuit of claim 12 , wherein each of said averaging stages comprises a plurality of amplifiers.
14. The clock generation circuit of claim 9 , wherein a phase of said multi-phase output clock is adjusted based on a phase selection control signal.
15. The clock generation circuit of claim 14 , wherein a rise/fall time of said phase selection control signal is longer than a frequency of said multi-phase output clock.
16. An integrated circuit, comprising:
a clock generation circuit for generating a multi-phase output clock, comprising:
a ring oscillator generating a plurality of clocks having a substantially similar frequency and different phases;
a plurality of amplifiers, each of said amplifiers amplifying two or more of said plurality of clocks;
a first adder for summing an output of a first set of said plurality of amplifiers to generate a first phase of said multi-phase output clock; and
a second adder for summing an output of a second set of said plurality of amplifiers to generate a second phase of said multi-phase output clock.
17. The integrated circuit of claim 16 , wherein each of said plurality of amplifiers comprises a differential pair circuit.
18. The integrated circuit of claim 17 , wherein said adder comprises the application of an output of said differential pair circuits to a load.
19. The integrated circuit of claim 16 , further comprising a plurality of averaging stages.
20. The integrated circuit of claim 19 , wherein each of said averaging stages comprises a plurality of amplifiers.