Low power vector summation method and apparatus
View Patent ↗An arrangement is provided for using 2's complement arithmetic without the high switching activity of the prior art. In particular, the invention operates to exploit the sign-extension property of a 2's complement number. A reduced representation for 2's complement numbers is provided to avoid sign-extension and the switching of sign-extension bits. The maximum magnitude of a 2's complement number is detected and its reduced representation is dynamically generated to represent the signal. A constant error introduced by the reduced representation is also dynamically compensated.
1. A method for operating an arithmetic processor comprising the steps of:
causing a magnitude of at least one coefficient of the arithmetic processor to be detected and the detected magnitude to be implemented in 2's complement reduced representation arithmetic; and
adding a compensation vector for the at least one coefficient at an end of an accumulation path for the arithmetic processor.
2. The method of claim 1 wherein all coefficients are implemented in 2's complement reduced representation arithmetic and a separate compensation vector generated for each coefficient, and further wherein a sum of all of the separate compensation vectors is added at the end of the accumulation path.
3. The method of claim 1 comprising the further step of:
dividing a set of taps of the arithmetic processor among a plurality of sections, wherein the 2's complement reduced representation for ones of the at least one coefficient corresponding to taps within a given section is arranged to have a sign bit at a common bit position.
4. The method of claim 3 wherein the division of the set of taps among a plurality of sections is arranged so that each section has an equal number of taps.
5. The method of claim 3 comprising the further step of detecting a maximum magnitude of coefficients corresponding to taps within a given section, wherein the common bit position for sign bits of coefficients for the given section is established based on the detected maximum coefficient magnitude.
6. The method of claim 5 comprising the further step of providing a common compensation vector for all taps in a given section, a value of the common compensation vector being determined in respect to the common sign bit position, and wherein a total compensation vector value for the given section is determined as a product of the common compensation vector and the number of taps in the given section.
7. The method of claim 3 comprising the further steps of:
computing a difference between the compensation vector determined for a given section based on the common sign bit position and a base compensation vector; and
combining the computed difference with a value of the base compensation vector at the end of the accumulation path.
8. The method of claim 7 wherein the combined computed difference and the value of the base compensation vector comprise the compensation vector added at the end of the accumulation path.
9. The method of claim 8 wherein the step of combining the computed difference further comprises:
computing a product of the determined difference and the number of taps for the given section;
summing products computed for each of the plurality of sections and combining the sum of products with the base compensation vector.
10. The method of claim 7 wherein the step of computing a difference further comprises:
determining a difference in bit position between a sign bit position for the base compensation vector and the common sign bit position for the given section.
11. The method of claim 1 wherein the arithmetic processor is implemented as a filter.
12. The method of claim 1 comprising the further steps of:
computing a difference between the compensation vector determined for the at least one coefficient and a base compensation vector; and
combining the computed difference with a value of the base compensation vector at the end of the accumulation path.
13. An arithmetic processing circuit having a plurality of taps comprising:
a partial product generator operative to generate a partial product in 2's complement reduced representation; and
logic means operating on bit positions of the partial product generator for detecting a sign bit thereof and causing the complementation of the sign bit.
14. The arithmetic processing circuit of claim 13 further comprising:
a detector for detecting a magnitude of ones of the reduced representation partial products; and
generation means for generating a compensation vector corresponding to the detected magnitude of the partial products.
15. The arithmetic processing circuit of claim 14 wherein the plurality of taps is divided among a plurality of equal-length sections and the detector further operates to detect a maximum magnitude of ones of the reduced representation partial products in a given section.